-
XLINX V5 芯片的DDR SDRAM参考设计
The xapp851.zip archive includes the following subdirectories. The specific
contents of each subdirectory below:
tl - HDL design files
sim - simulation files
synth - Synthesis related files
par - Place/Route related files
以及DDR SDRAM控制器设置.pdf文件
- 2023-08-29 16:40:03下载
- 积分：1
-
Marquee procedures described in VHDL, for beginners to practice
VHDL描述的跑马灯程序，用于初学者练习-Marquee procedures described in VHDL, for beginners to practice
- 2022-05-27 22:24:01下载
- 积分：1
-
mp3codec
it is used to compile codec
- 2009-03-04 17:00:53下载
- 积分：1
-
MIPSTOP
说明： misp顶层文件，verilog实现misp架构，并且支持modelsim仿真(Verilog implements MISP architecture and supports Modelsim simulation)
- 2020-06-18 04:40:02下载
- 积分：1
-
dds_test
说明： 直接数字式频率合成器DDS设计、Verilog。
产生的信号可以是正弦波或方波、三角波、锯齿波等，自选。
采用DDS技术，将所需生成的波形写入ROM中，按照相位累加原理合成任意波形。
此方案得到的波形稳定，精度高，产生波形频率范围大，容易产生高频。
本实验在设计的模块中，包含以下功能：
（1）通过 freq 信号输入需要的频率的值；
（2）通过 wave_sel 信号选择所需的波形；
（3）通过 amp_adj 信号选择波形放大的倍数。(DDS design of direct digital frequency synthesizer, Verilog.
The generated signal can be sinusoidal or square wave, triangular wave, sawtooth wave and so on, optional.
By using DDS technology, the required waveforms are written into ROM, and arbitrary waveforms are synthesized according to the principle of phase accumulation.
The waveform obtained by this scheme is stable, accurate and easy to generate high frequency waveform.
This experiment includes the following functions in the designed module:
(1) Input the required frequency value through freq signal;
(2) Choosing the required waveform by wave_sel signal;
(3) Select the multiplier of waveform amplification by amp_adj signal.)
- 2019-01-19 16:07:50下载
- 积分：1
-
sph-original-codes
SPH的原始代码，希望可以帮到大家啊关于模拟poiseuille的(simulate poiseuille fuild)
- 2020-10-22 10:27:23下载
- 积分：1
-
6_USB_to_SDHC_Lab
altera max10 USB demo，使用了phy，把开发板配置成U盘模式(altera max10 USB demo，using PHY device，design a U pan)
- 2015-10-22 20:47:49下载
- 积分：1
-
CAN总线开发代码 can-sja1000
CAN总线开发代码，FPGA与sja1000通信，可实现CAN的接收和发送。(The FPGA and the sja1000 CAN bus development code, communication, which CAN realize the CAN send and receive.)
- 2021-04-14 17:08:55下载
- 积分：1
-
weitongbu
基于fpga的位同步信号提取仿真 使用vhdl语言 quartus(To use vhdl language quartus fpga bit synchronization signal extraction-based simulation)
- 2020-12-29 17:29:00下载
- 积分：1
-
VHDL_ 两个电路计数上 / 下液晶显示语言 VHDL (海 mạch đếm lên/xuống hiển 施耐液晶 bằng ngôn ngữ VHDL)
VHDL_ 两个电路计数上 / 下液晶显示语言 VHDL (海 mạch đếm lên/xuống hiển 施耐液晶 bằng ngôn ngữ VHDL)
- 2022-02-03 20:36:30下载
- 积分：1
