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steper motor
stepper motor module on spartan 6 and 24MHz clock fequency
- 2019-03-10 15:44:31下载
- 积分:1
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zidongmen1
说明: 控制步进电机转动,正反转,旋转角度完美掌握。很好用,亲测(Control stepping motor rotation, positive and negative rotation, perfect control of rotation angle. Very easy to use, personal test)
- 2018-12-25 16:41:07下载
- 积分:1
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DDS
说明: 使用Verilog,以Quartus II 为平台,编写了一个DDS信号发生器程序。(Using Verilog and Quartus II as the platform, realizing the DDS signal generator program .)
- 2020-11-26 17:12:26下载
- 积分:1
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OFDM_CP
ofdm系统的matlab实现,包括插入导频信号和循环前缀(Matlab implementation of ofdm system, including inserted pilot frequency signal and the cyclic prefix)
- 2013-05-29 10:10:23下载
- 积分:1
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altera fpga verilog 设计的基于查找表的DCT程序及zigzag扫描程序,已经过matlab 和modelsim
验证,文件中包含TEST...
altera fpga verilog 设计的基于查找表的DCT程序及zigzag扫描程序,已经过matlab 和modelsim
验证,文件中包含TESTBENCH ,直接可用-altera fpga verilog design table DCT-based search procedures and zigzag scanning procedures, and ModelSim matlab has been verified, the document contains TESTBENCH, directly available
- 2022-05-31 13:50:54下载
- 积分:1
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GgmsskModulatM
GMSK的调制解调,理理想信道,画出其功率谱。
(GMSK modulation and demodulation, management ideal channel, to draw its power spectrum.)
- 2020-07-02 02:00:02下载
- 积分:1
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alu
verilog code for 8 bit alu
- 2015-06-30 18:49:10下载
- 积分:1
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使用FPGA的FIFO,状态机,乒乓操作等实现了异步UART。
使用FPGA的FIFO,状态机,乒乓操作等实现了异步UART。-The use of FPGA-FIFO, state machine, ping-pong operation to achieve the asynchronous UART.
- 2022-12-07 20:00:03下载
- 积分:1
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fpgaaverilogamaxamin
verilog 编写的比较最大值最小值得的程序,而且能够求出最大最小值在ram中存储的位置,测试通过下载即用(Comparison of the maximum write verilog smallest worthwhile program, and minimum and maximum values can be obtained is stored in ram position, the test that is used by downloading)
- 2013-06-06 15:44:48下载
- 积分:1
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QAM发生仿真
在Qaurtus环境下用Verilog输入实现64QAM信号的发生,用MATLAB协助验证,观察了PN序列对应的星座图。(Simulating generation of 64QAM RF Signal in Quartus II IDE,identified with MATLAB,constellation gram displayed.)
- 2021-03-02 23:39:33下载
- 积分:1