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基于VHDL语言的循环码编码器的程序,以一个(15,6)循环码为例...
基于VHDL语言的循环码编码器的程序,以一个(15,6)循环码为例-VHDL language based on the cycle of the program code encoder to a (15,6) cyclic code as an example
- 2022-03-13 14:13:18下载
- 积分:1
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cic
说明: 五阶CIC梳状积分滤波器,可以综合,非常有参考价值(Fifth-order CIC points comb filter, can be integrated and very useful)
- 2008-11-17 12:57:01下载
- 积分:1
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标准SDR SDRAM控制器参考设计,Lattice提供的verilog源代码
标准SDR SDRAM控制器参考设计,Lattice提供的verilog源代码-standard SDR SDRAM controller reference design, the Lattice Verilog source code
- 2022-03-18 08:05:11下载
- 积分:1
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4
Verilog的135个经典设计实例.使你工作使用学习中,会有很大帮助,各种典型案例(135 classic Verilog design examples. Make your work with the study, will be of great help, of various typical cases
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- 2014-03-19 10:55:14下载
- 积分:1
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3-8
3-8译码器,可以讲三位二进制输入转换为8中取1的输出信号(3-8 decoder, you can talk about the three binary input is converted to 8 of the output signal from 1)
- 2009-07-16 17:23:30下载
- 积分:1
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RDA1846
rda1846 + pic18f2552 usb circuit schematic.
- 2012-09-12 20:05:38下载
- 积分:1
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code
code for booths multiplier
- 2009-03-15 09:35:26下载
- 积分:1
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adder
This the adder VHDL code, it contains input and output fild, also simulate file-adder
- 2022-06-21 18:48:32下载
- 积分:1
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freq_meter
使用verilog写的频率计,可切换档位(Frequency counter using verilog write switch stalls)
- 2012-12-08 00:54:56下载
- 积分:1
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异步FIFO的设计 包括testbench 已调试成功
异步FIFO的设计 包括testbench 已调试成功-Asynchronous FIFO design includes testbench debug success has been
- 2023-04-13 19:40:03下载
- 积分:1