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7_ImageEnhance
基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,图像增强处理,平滑,锐化,滤波(System Generator based image processing engineering, multimedia processing FPGA implementation source code, image enhancement, smoothing, sharpening, filtering)
- 2020-10-20 21:07:24下载
- 积分：1
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8位大小比较器
说明： 8位大小比较器的VHDL源代码，Magnitude Comparator
VHDL description of a 4-bit magnitude comparator with expansion inputs(eight compared with the size of the VHDL source code, Magnitude Comparator VHDL description of a 4-bit magnitude comparator inputs with expansion)
- 2005-10-28 22:35:12下载
- 积分：1
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G.hnMAC层功能代码MPDU ASSEMBLER
G.hnMAC层功能代码，实现了MPDU的资源调度(G.gn MAC codeG.gn MAC codeG.gn MAC code)
- 2011-05-18 11:23:08下载
- 积分：1
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这是8位微处理器的Verilog源代码，可以欠在Flex10k10里面
这是8位微处理器的Verilog源代码，可以欠在Flex10k10里面-This is the 8-bit microprocessor Verilog source code, can they owed in Flex10k10
- 2022-02-06 13:26:07下载
- 积分：1
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craps
this is the source code we have been working on for our project using altera de2 board. the code can be run but some of it miss the end game module, while some doesn t have the complete vga code
- 2014-05-20 15:21:23下载
- 积分：1
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55593402DDS_vhdl
DDS分频实现，全部代码的完整过程，包括截图等(DDS divider to achieve the complete process of all the code)
- 2013-05-15 16:49:55下载
- 积分：1
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树式除法型开方器VERILOG实现,用于任意长度的无符号数的开方运算...
树式除法型开方器VERILOG实现,用于任意长度的无符号数的开方运算-Square root of the tree-type divider-type device to achieve VERILOG
- 2022-09-04 14:20:03下载
- 积分：1
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add
流水线乘法器与加法器
开发环境：Modelsim（verilog hdl）(Multiplier and adder pipeline development environment: Modelsim (verilog hdl))
- 2009-05-18 12:19:24下载
- 积分：1
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FPGA_Book_cd
《无线通信FPGA设计》包含的所有例子源码，包括matlab仿真和verilog源码，本书内容还是非常丰富的，涉及无线通信领域各个方面。不过对于一些比较新的技术，其FPGA实现部分过于简略，难以在工程中实用化。(" Wireless FPGA Design" contains all the examples source code, including the matlab simulation and verilog source code, the contents of this book is still very rich, involved in all aspects of the field of wireless communications. But for some relatively new technology, some of its FPGA implementation is too brief, it is difficult in practical engineering.)
- 2009-10-26 14:50:33下载
- 积分：1
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4-16.doc
4-16译码器，用VHDL编写的，可以直接下载到可编程逻辑器件中(4-16 decoder, written with VHDL, can be directly downloaded to the programmable logic device)
- 2010-11-24 15:13:14下载
- 积分：1
