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FUZZY
verilog 模糊PID 通过修改MIF文件 可以完成单个参数整定(FUZZY pid by verilog HDL)
- 2020-08-05 09:18:34下载
- 积分:1
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Chapter10
第十章的代码。
本书通过100多个模块实例,详细地讲解了Verilog HDL程序设计语言,全书共分13章,内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等,实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench,所举实例具有很强的实用性和代表性,每个实例均给出了介绍、功能分析、程序代码和结果演示(Chapter X code. This book by more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of additions device/counters, multipliers/dividers, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and the results demonstrate)
- 2009-11-17 13:52:32下载
- 积分:1
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Reread-machine-program
通过凌阳16位单片机实现复读机的应用的程序。(By Sunplus 16-bit MCU repeater application process.)
- 2011-07-30 16:09:07下载
- 积分:1
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整个工程代码
掌握SDRAM数据读写、刷新、初始化以及FPGA串口收发时序,熟练FIFO IP核的生成和调用。(Master SDRAM data read and write, refresh, initialization and the timing of sending and receiving of the serial port of the FPGA, skilled in the generation and invocation of the FIFO IP core.)
- 2019-01-21 17:21:27下载
- 积分:1
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CPU-Verilog
说明: 简单流水线CPU,使用 verilog实现,实现一条指令的整个流程(Implementation of Simple Pipeline CPU Verilog)
- 2020-06-23 19:40:01下载
- 积分:1
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State.Machine.Coding.Styles.for.Synthesis(状态机,英文,VHDL)
State.Machine.Coding.Styles.for.Synthesis(状态机,英文,VHDL)-State.Machine.Coding.Styles.for.Synthesis (FSM, English, VHDL)
- 2023-06-02 11:25:02下载
- 积分:1
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FFT
64-point FFT/IFFT processor
architecture : Rrdix-SDF
- 2013-01-13 06:29:57下载
- 积分:1
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or2a
使用vhdl语言设计一位全加器,在仪器上下载并实现LED灯的闪亮(A full adder design)
- 2013-09-26 18:24:15下载
- 积分:1
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HDLC控制器
HDLC控制器源码,包括单独HDLC的Tx端和Rx端实现,以及顶层带FIFO和Wishbone总线控制器的实现,通过Wishbone可方便与CPU连接,通过软件控制整个HDLC控制器的工作。
- 2023-06-14 17:55:03下载
- 积分:1
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ISP的IP核,下载即可用,解压到指定目录下就可以了,参照里面的read me....
ISP的IP核,下载即可用,解压到指定目录下就可以了,参照里面的read me.-ISP of the IP core, can be used to download, unzip to the specified directory can be a light inside the read me.
- 2022-02-02 17:09:38下载
- 积分:1