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y210
三八译码器,四位加法器,EDA实验,用verilog编写(EDA experiment with verilog language)
- 2017-10-30 20:14:30下载
- 积分:1
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spi转i2s的verilog程序,fpga是总模块,spi和i2s是子模块,shiftreg是转换...
spi转i2s的verilog程序,fpga是总模块,spi和i2s是子模块,shiftreg是转换-spi transfer i2s the verilog program, fpga is the total module, spi, and i2s is the sub-module, shiftreg is to convert
- 2022-02-13 16:18:27下载
- 积分:1
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Tft good reference is listed, eight general
很好的tft参考实列,通用的8位并口,非常快移值-Tft good reference is listed, eight general-purpose parallel port, very fast shift value
- 2022-03-19 11:01:47下载
- 积分:1
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xilinx of ddr sdram controller documentation
xilinx的ddr sdram控制器文档-xilinx of ddr sdram controller documentation
- 2023-04-17 06:40:03下载
- 积分:1
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sqrt_pipeline
说明: Matlab - to hdl code for square root
- 2020-06-17 12:20:02下载
- 积分:1
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6264
6264是一种8K×8的静态存储器.SRAM 的典型芯片有2KB 的6116、8KB 的6264 以及32KB的62256,其中6264 芯片应用最为广泛.(6264 is the 62256 typical chip SRAM.SRAM a 8K* 8 with 2KB 6116, 8KB 6264 and 32KB 6264 chip, which is most widely used.
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- 2015-02-01 13:28:11下载
- 积分:1
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sha1_v01
基于FIPS 180-4标准的SHA-1算法的verilog HDL实现,分模块分别实现(FIPS 180-4 standard SHA-1 algorithm-based verilog HDL sub-modules, respectively, to achieve)
- 2012-09-20 14:57:19下载
- 积分:1
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TrafficLight
利用Verilog编写一个交通灯控制电路,能控制两条路上红、黄、绿灯的变化,并且显示等待时间(Using Verilog HDL to design a traffic light control circuit. It can control the change of red, yellow and green lights on two roads, and display the remaining waiting time.)
- 2018-11-22 23:07:33下载
- 积分:1
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spi_interface
说明: spi通用串行总线,4线控制,可读写操作(SPI universal serial bus, 4-wire control, readable and writable operation)
- 2019-04-29 12:37:55下载
- 积分:1
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DA
说明: DOCUMENT ON DISTRIBUTED ARITHMATIC
- 2014-02-05 17:06:51下载
- 积分:1