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alu
说明： 用Verilog编写的简单的运算单元（ALU），可实现加、减、与、或、异或、非、左、右移等功能(Verilog prepared with simple arithmetic unit (ALU), can be add, subtract, and, or, exclusive-OR, non-, left, and other functions shifted to right)
- 2009-07-28 16:20:52下载
- 积分：1
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23565785scan_led
Quartus环境下的7段扫描显示电路的源程序(Quartus environment of the seven scanning display circuit of the source)
- 2006-12-11 17:11:41下载
- 积分：1
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BCHencodeanddecode
bch 编码和译码，用硬件语言vhdl实现(bch edcode and decoder)
- 2020-06-28 18:00:01下载
- 积分：1
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traffic
说明： 模拟交通灯
verilog CPLD
EPM1270
源代码(Simulation of traffic lights verilog CPLDEPM1270 source code)
- 2008-10-30 23:12:20下载
- 积分：1
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Fractional_Time_Delay
Used for Time shifting discrete signals, it can do both integral and fractional sampling period delay. Original.
- 2020-12-16 22:29:12下载
- 积分：1
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FFT_verilog
verilog 实现的FFT 流水线操作，速度能达到200M(verilog pipelining the FFT implementation, the speed can reach 200M)
- 2021-03-23 09:29:15下载
- 积分：1
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frequency divider
说明： FPGA对系统50M时钟进行分频。FPGA最基本功能基础(FPGA Verilog program, key detection, program jitter elimination, jitter elimination, delay detection keys)
- 2019-04-27 23:35:12下载
- 积分：1
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1_Carm
说明： 经典的OV5642的verilog驱动程序(Verilog Driver of Classic OV5642)
- 2019-03-19 13:38:29下载
- 积分：1
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project1
使用system verilog编写的一系列代码。包括二进制码与格雷码转换，优先编码器，38解码器，计数器等等(system verilog code with testbench.)
- 2020-06-23 08:20:02下载
- 积分：1
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THS1206
FPGA来实现数据采集，AD采用TI公司的THS1206，高速并行AD，内含16字FIFO，降低硬件复杂度。(FPGA to realize data acquisition, AD using TI company s THS1206, high-speed parallel AD, containing the 16-character FIFO, to reduce hardware complexity.)
- 2009-07-09 09:08:27下载
- 积分：1
