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facman
一款在Verilog实现的吃豆人游戏,采用VGA接口,在Nexys3开发板上运行无误。(A pac-man game implemented via Verilog, using VGA interface, perfectly run on Nexys 3)
- 2021-03-31 07:39:09下载
- 积分:1
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1-Quadrature_decoder
说明: 光栅尺FPGA调试程序,本人亲自调试保证可用(Grating ruler FPGA debugging program)
- 2019-12-31 23:23:11下载
- 积分:1
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sph-original-codes
SPH的原始代码,希望可以帮到大家啊关于模拟poiseuille的(simulate poiseuille fuild)
- 2020-10-22 10:27:23下载
- 积分:1
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exercise3
用verilog实现dsp与Fpga接口的同步设计,其功能包括读写操作及四个功能模块,采用两个fifo实现不同时钟域的地址与数据的转换,在quartus ii11.0环境下运行,运行此程序之前需运行将调用fifo。(Dsp using verilog achieve synchronization with Fpga interface design, its features include read and write operations and four functional modules, using two different clock domains to achieve fifo address and data conversion in quartus ii11.0 environment to run, run this program required before running calls fifo.)
- 2013-08-30 11:12:09下载
- 积分:1
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cpu_easy
说明: ADD MOV MOVi SUB四指令cpu设计,qutartus,(Design of four-instruction CPU)
- 2019-05-13 11:44:49下载
- 积分:1
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sdcard_mass_storage_controller
A host controlled ot control sd cards
- 2021-04-29 13:58:43下载
- 积分:1
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wave_coif3
滤波器的实现,总共为4种,是简单的coif3滤波器的实现方法(The implementation of the filter, a total of 4, is a simple coif3 filter implementation method)
- 2018-03-24 21:05:14下载
- 积分:1
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FPGASquare-RootRaised-CosineFilter
数字通信系统中, 基带信号的频谱一般较宽, 因此
传递前需对信号进行成形处理, 以改善其频谱特性,使
得在消除码间干扰与达到最佳检测接收的前提下,提高信道的频带利用率。目前,数字系统中常使用的波形成形滤波器有平方根升余弦滤波器、 高斯滤波器等。设计方法有卷积法或查表法, 其中: 卷积法的实现,需要消耗大量的乘法器与加法器,以构成具有一定延时的流水线结构。为降低硬件消耗,文献提出了一种分(FPGA Implementation of Square Root Raised Cosine Pulse Shaping Filter)
- 2011-05-04 21:23:36下载
- 积分:1
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57578865dac_sigma_delta
对delta sigma进行设计,实现delta sigma ADC的设计(this is use for delta sigma adc ,and design and achieve adc)
- 2020-06-16 14:40:01下载
- 积分:1
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AD9267的FPGA参考设计
AD9267 10bit 640MSPS高速ADC的FPGA参考设计
Verilog语言实现
包含Xilinx ISE12.2工程
- 2023-01-04 17:30:03下载
- 积分:1