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ddr_for_controller_and_phy
说明: 这是本人曾经参与的一个DDR controller接口项目,主要是FPGA rtl实现,仅供参考。(This is a DDR controller interface project that I once participated in, mainly implemented by FPGA RTL, for reference only.)
- 2020-12-21 20:59:08下载
- 积分:1
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利用fpga实现的DDS,可输出正弦波,输出频率可调
利用fpga实现的DDS,可输出正弦波,输出频率可调-FPGA realization of the use of DDS, sine wave output, output frequency adjustable
- 2022-01-28 18:28:31下载
- 积分:1
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wireless
基于FPGA DE0以及niosII的射频无线发送程序,采用spi接口操作无线模块nrf24l01(To spi interface operation wireless module nrf24l01 of FPGA DE0, as well niosII RF wireless transmitter program)
- 2012-12-02 22:46:14下载
- 积分:1
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UART_RX_
说明: fpga串口的发送程序基于verilog语言拿走不用谢。(The sending program of FPGA serial port is based on Verilog language.)
- 2020-06-18 04:00:01下载
- 积分:1
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SoC-Design-DDR3-Controller-master
说明: 难得的soc设计用的ddr3 verilog,可用于学习!!!!!有datasheet ,可仿真(soc ddr3 verilog for study !!)
- 2020-06-22 17:07:57下载
- 积分:1
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Turbo Decoder Release 0.3
Turbo Decoder Release 0.3
* Double binary, DVB-RCS code
* Soft Output Viterbi Algorithm
* MyHDL cycle/bit accurate model
* Synthesizable VHDL model
-Turbo Decoder Release 0.3* Double binary, DVB-RCS code* Soft Output
Viterbi Algorithm* M yHDL cycle/bit accurate model* Synthesizable VHDL
model
- 2022-01-30 12:47:05下载
- 积分:1
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Digital Cymometer VHDL procedures and simulation of the file name: plj.vhd.
数字频率计VHDL程序与仿真
文件名:plj.vhd。
--功能:频率计。具有4位显示,能自动根据7位十进制计数的结果,自动选择有效数据的
--高4位进行动态显示。小数点表示是千位,即KHz。
-Digital Cymometer VHDL procedures and simulation of the file name: plj.vhd.- Function: frequency meter. With four shows that will automatically count seven decimal results, automatic selection of effective data- four for the high dynamic display. Decimal point that is 1000, or KHz.
- 2022-08-04 07:22:59下载
- 积分:1
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脉动进位加法器
设计的结构是纹波进位加法器,但执行的操作是加法和减法,两种操作都是32位的,具体取决于控制信号。如果控制信号为“1”,则选择减法,然后选择“0”,然后选择加法
- 2022-02-02 17:58:16下载
- 积分:1
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Marquee procedures described in VHDL, for beginners to practice
VHDL描述的跑马灯程序,用于初学者练习-Marquee procedures described in VHDL, for beginners to practice
- 2022-05-27 22:24:01下载
- 积分:1
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六层的电梯控制系统
用VHDL描述同时还附有系统仿真图形
六层的电梯控制系统
用VHDL描述同时还附有系统仿真图形
- 2022-07-25 01:03:55下载
- 积分:1