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EDA
EDA-Verilog 编码原则,初学者必看!-EDA-Verilog coding principles, beginners must-see!
- 2022-02-20 01:38:26下载
- 积分:1
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cnt24_t
这是二十四进制计数器的源程序,有需要的同学可以参照一下!(This is 24 hexadecimal counter source, needy students can refer to you!)
- 2008-12-22 09:29:29下载
- 积分:1
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VHDL 0~
程序用VHDL实现:
利用一秒定时测量频率
并且显示,范围0~-VHDL 0~
- 2022-05-15 03:55:50下载
- 积分:1
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用VHDL 编写的一个16位的cpu 设计方案,可以执行8条指令。
用VHDL 编写的一个16位的cpu 设计方案,可以执行8条指令。-use VHDL to prepare a 16 cpu design of the program, the implementation of eight instructions.
- 2023-07-06 05:40:03下载
- 积分:1
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bootstrap_ace_v1.3.2
多年项目经验测试文档测试文档,重要保存重要保存重要保存重要保存重要保存重要保存(Years of project experience testing document testing, it is important to save save save important important important important to save save save important)
- 2016-03-05 15:46:27下载
- 积分:1
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FPGA控制AG9226代码
FPGA控制AG9226进行采样的代码,并用signaltap测试了一下其正确性
- 2022-07-21 15:41:56下载
- 积分:1
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1.初始状态为4个方向的红灯全亮,时间1秒。
2.东、西方向绿灯亮,南、北方向红灯亮。东、西方向通车,时间30秒。
3.东、西方向黄灯闪烁,南、北方...
1.初始状态为4个方向的红灯全亮,时间1秒。
2.东、西方向绿灯亮,南、北方向红灯亮。东、西方向通车,时间30秒。
3.东、西方向黄灯闪烁,南、北方向红灯亮。时间2秒。
4.东、西方向红灯亮,南、北方向绿灯亮。南、北方向通车,时间15秒。
5.东、西方向红灯亮,南、北方向黄灯闪烁。时间2秒。
6.返回2,继续运行。
-1. Initial state for four whole direction of the red lights lit up, a second time. 2. East and West to the green, in the south, north to the red light. West and the East to open in time for 30 seconds. 3. East and West to the blinking yellow light, in the south, north to the red light. Time 2 seconds. 4. East and West to the red light, in the south, north to the green. South and North to the opening time of 15 seconds. 5. East and West to the red light, in the south, north to the flashing yellow light. Time 2 seconds. 6. Return 2, continued to operate.
- 2023-01-12 03:20:04下载
- 积分:1
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Spartan-3E_Starter_Kit
Spartan® -3E 现场可编程门阵列家族是为满足对成本敏感的消费电子大量应用的需要
而特别设计的。
(Field Programmable Gate Array family needs is to meet the cost-sensitive applications, a large number of consumer electronics
Specially designed.)
- 2014-07-10 21:30:34下载
- 积分:1
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ANALYSIS-OF-FULL-ADDER
DESCRIPTION OF FULL ADDER
- 2013-11-12 13:32:19下载
- 积分:1
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VHDL3
说明: 一个使用VHDL进行正弦波信号产生的历程,非常有用。(A sine wave signal generator using VHDL for the course, very useful.)
- 2010-03-27 09:18:41下载
- 积分:1