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Xilinx ISE 8.2i s license
Xilinx ISE 8.2i的license-Xilinx ISE 8.2i s license
- 2023-06-08 10:45:03下载
- 积分:1
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Modulator70
个人参与的某国家工程并行排序MATLAB程序,用于FPGA的RTLAB仿真,使用Simulink工具生成HDL代码。测试可用。(Individuals involved in sort of a national engineering parallel MATLAB programs for the FPGA RTLAB simulation, using the Simulink tool to generate HDL code. Test available.)
- 2011-07-29 15:16:30下载
- 积分:1
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29335-素材(代码)
说明: 基于fpga的数字图像处理原理及应用源码(The principle and source code of digital image processing based on FPGA)
- 2020-07-02 05:00:02下载
- 积分:1
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add
流水线乘法器与加法器
开发环境:Modelsim(verilog hdl)(Multiplier and adder pipeline development environment: Modelsim (verilog hdl))
- 2009-05-18 12:19:24下载
- 积分:1
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Foundry-Flash-Verilog-code
几大代工厂的flash verilog源代码(flash verilog code)
- 2021-03-09 15:29:28下载
- 积分:1
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完成的是RS422信号的计数功能,并产生一定的触发信号
完成的是RS422信号的计数功能,并产生一定的触发信号-RS422 signals the completion of the count function, and produce a certain trigger signals
- 2022-04-14 14:08:50下载
- 积分:1
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MIPS
Top level Architecture of MIPS Processor
- 2009-08-17 21:08:17下载
- 积分:1
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done, would not have introduced the document on the bar, IEEE1364 standard (open...
做EDA的,就不用介绍这个文件了吧,IEEE1364标准(开放)。-done, would not have introduced the document on the bar, IEEE1364 standard (open).
- 2022-03-25 09:59:57下载
- 积分:1
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verilog源码,可实现两位的加法器,在xillinx foundation 3.1下验证通过...
verilog源码,可实现两位的加法器,在xillinx foundation 3.1下验证通过-verilog source, the two can achieve Adder, In xillinx foundation 3.1 certification through
- 2022-10-11 18:55:03下载
- 积分:1
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ofdm_quartus_v72
说明: OFDM的简易verilog仿真程序,环境是quartus,版本需要7.2以上(OFDM Modulation and Demodulation using Verilog in Quartus)
- 2009-08-30 21:58:25下载
- 积分:1