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FPGA_flash设计
我们的设计是用一个FSM控制器来控制发送什么命令，flash模块判断FSM发送过来的state信号来选择应该执行什么操作，当命令写入或者读出后，会发送一个flag_done命令，这个命令让我们判断上个指令是否完成，如果完成后FAM将发送下一个命令.(Our design uses a FSM controller to control what commands are sent. The flash module judges the state signal sent by the FSM to select what operation should be performed. When the command is written or read out, a flag_done command is sent. This command lets us judge whether the last word is finished or if the FAM will be sent after completion. The next command)
- 2018-04-21 21:37:17下载
- 积分：1
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Source code for asyn_fifo using verilog language.
异步FIFO 设计源代码，内涵完整的verilog源代码和测试代码。-Source code for asyn_fifo using verilog language.
- 2022-04-14 15:20:53下载
- 积分：1
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4通道12位AD芯片 AD7862控制模块,VHDL源代码,适于单次转换采样,250K采样率....
4通道12位AD芯片 AD7862控制模块,VHDL源代码,适于单次转换采样,250K采样率.-4-channel 12-bit AD chip AD7862 control module, VHDL source code, suitable for single conversion sampling, 250K sampling rate.
- 2022-04-20 03:37:20下载
- 积分：1
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20181060261-李康_3
说明： 秒表的实现，有暂停清零功能，Quartus II(Stopwatch realization, has the pause clear function)
- 2020-12-26 15:56:03下载
- 积分：1
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FIFO
fifo程序代码，程序编写，测试仿真图形，方便，比较实用(fifo code, programming, testing, simulation graphics, convenient and more practical)
- 2016-03-16 10:06:12下载
- 积分：1
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VHDL与源代码包
VHDL与源代码包-and VHDL source code
- 2022-04-27 02:45:55下载
- 积分：1
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A comparison reference value has sram IP core, on the SOPC interested people hav...
一个比较有参考价值的sram IP核，对SOPC感兴趣的人士有一定的指导意义！该程序是采用avalon总线，可以直接内嵌进SOPC Builder。-A comparison reference value has sram IP core, on the SOPC interested people have a certain guide! The procedure is used avalon bus, can be directly embedded into the SOPC Builder.
- 2022-05-18 11:22:45下载
- 积分：1
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cycloneIII_3c120_dev_power_demo
cycloneIII_3c120_dev_power_demo atlera公司官方例程(cycloneIII_3c120_dev_power_demo atlera company official routines)
- 2014-12-15 17:09:14下载
- 积分：1
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A complete signal test procedures, the various indicators of signal integrity te...
一个完整的信号测试程序,对信号的各项指标进行完整的测试,并分析-A complete signal test procedures, the various indicators of signal integrity testing, and analysis of
- 2022-03-23 02:41:40下载
- 积分：1
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MB
说明： 基于VHDL语言数字秒表设计,在FPGA实验平台下开发(Digital stopwatch design based on VHDL, FPGA experimental platform under development)
- 2015-04-21 20:11:14下载
- 积分：1
