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ymq.ppt.tar
掌握二-十进制(BCD码)异步计数器的工作原理和设计方法；
掌握中规模集成二-五-十进制异步计数器74LS90的功能及其应用；(Master II- Decimal (BCD code) the principle and an asynchronous counter design grasp the scale of integration in two- five- Decimal asynchronous counter 74LS90 features and applications )
- 2011-04-26 21:53:37下载
- 积分：1
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verilog写的数字频率计的显示模块,可以
verilog写的数字频率计的显示模块,可以-written in Verilog Digital Cymometer display module can be
- 2022-03-23 18:10:33下载
- 积分：1
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TugasUAS_AuditTI_1504505017_Reguler
说明： ertyguhijop[lkjhvbn hiouopi][[poiuy
- 2019-02-05 09:18:23下载
- 积分：1
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pj2-NO.6
基于FPGA的电子密码锁设计-已在开发板上成功运行，通过老师检验。(FPGA based electronic password lock design- has been successfully developed on the development board, through the teacher inspection.)
- 2017-05-26 11:54:44下载
- 积分：1
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20071026_091831_632
SOPC基于MATLAB与DSP Builder设计技术
实验使用说明，非常详细，易于上手(dsp builder)
- 2009-04-01 14:44:16下载
- 积分：1
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altera的关于对数计算的IP core。
altera的关于对数计算的IP core。-altera calculated on the logarithm of the IP core.
- 2022-09-17 13:25:03下载
- 积分：1
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freq_meter
FPGA的测频程序，用了D触发器，能测1hz到几百hz(FPGA frequency measurement procedures, using a D flip-flop, can be measured to a few hundred hz 1hz)
- 2016-04-03 13:41:48下载
- 积分：1
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SDRAM控制器源码，内含完整的控制器verilog源代码和测试代码，超值哈。...
SDRAM控制器源码，内含完整的控制器verilog源代码和测试代码，超值哈。-This readme file for the SDR SDRAM Controller includes information that was not
incorporated into the SDR SDRAM Controller White Paper v1.1.
- 2023-07-19 13:10:03下载
- 积分：1
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rtl
基于脉动结构的有限域乘法器，verilog代码(Based on the pulse of the structure of finite field multipliers, verilog code)
- 2010-01-04 11:48:50下载
- 积分：1
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xapp265
High-Speed Data Serialization and
Deserialization(840 Mb/s LVDS)
for xilinx fpga
- 2010-03-16 16:25:41下载
- 积分：1
