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Project_Gbit
pc与fpga之间通过千兆以太网交换机实现网络通信(Network communication between PC and FPGA via Gigabit Ethernet switch)
- 2020-06-17 20:40:04下载
- 积分:1
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北大verilog课件,数字集成电路设计入门,从HDL到版图
北大verilog课件,数字集成电路设计入门,从HDL到版图-North Verilog courseware, digital IC design entry, from HDL to the map
- 2022-07-24 16:14:44下载
- 积分:1
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这是我对FPGA程序的VME总线接口的设计,对FPGA的一面…
这是本人设计的一个关于VME总线接口的FGPA程序,FPGA一边连接ARM LPC2294,一边连接VME总线,FPGA采用的XILINX公司的SPARTANII系列,程序包包含完整的工程文件-This is my design of a VME bus interface on the FGPA procedures, FPGA side of the connection ARM LPC2294, while connecting VME bus, FPGA using the XILINX Inc. SPARTANII series, the package contains a complete project file
- 2023-01-09 16:20:04下载
- 积分:1
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proj-ASC
simple microprocessor that gives the greatest common divisor of 2 (4bit) numbers
- 2014-11-05 06:32:53下载
- 积分:1
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VHDL实现的读取和写入SDRAM的程序代码,学习的人可以参考下
VHDL实现的读取和写入SDRAM的程序代码,学习的人可以参考下-VHDL implementation SDRAM read and write program code, can refer to the following study
- 2023-03-19 17:05:04下载
- 积分:1
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Verilog_add_div_multi_exp
使用verilog写的32位浮点数加法模块、浮点数乘法模块、浮点数除法模块、浮点数指数模块。指数模块是综合前面三个例化成泰勒级数求指数,迭代次数(可设置)决定了精度。(Use verilog write 32-bit floating-point addition module, floating-point multiplication module, floating-point division module, the floating point number index module.Index module is a comprehensive index of the front three cases into Taylor series for calculating index, the number of iterations can be set to determine the precision)
- 2020-12-18 09:49:10下载
- 积分:1
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全部通过,是我的精心设计,完全满足初学者的要求。
全部通过,是我的精心设计,完全满足初学者的要求。-all passed, I was carefully designed, fully meet the requirements of beginners.
- 2022-03-02 01:44:58下载
- 积分:1
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接口键盘和液晶屏上AT89S52代码
接口键盘和液晶屏上AT89S52代码
- 2022-04-22 04:25:15下载
- 积分:1
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在MAXPLUSII下实现BOOTH算法,可以进行任意位K×K的乘法
在MAXPLUSII下实现BOOTH算法,可以进行任意位K×K的乘法-BOOTH algorthim implemented in the MAXPLUSII environment, which can carry out arbitrary bits multiplication.
- 2022-05-08 13:11:29下载
- 积分:1
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viterbi
维特比译码,卷积编码,verilog编写,2,1,2编码(Victor than decoding, convolution code, verilog write, 2,1,2 coding
)
- 2011-12-08 23:10:45下载
- 积分:1