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shumaguandongtai
VHDL的动态扫描显示六个数码管，包含分频代码产生25kHz的扫描信号作为时钟。(VHDL dynamic scanning display six digital tube contains 25kHz scanning signal is generated as a clock divider code.)
- 2012-11-26 14:40:42下载
- 积分：1
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adder
This the adder VHDL code, it contains input and output fild, also simulate file-adder
- 2022-06-21 18:48:32下载
- 积分：1
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一个用于锁相环开发的资料，请作为参考！
一个用于锁相环开发的资料，请作为参考！-A phase-locked loop for the development of the information, please as a reference!
- 2022-11-15 16:30:03下载
- 积分：1
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uart串行口,用Verilog编写的.供大家参考
uart串行口,用Verilog编写的.供大家参考-uart serial port, using Verilog prepared. For your reference
- 2022-07-17 22:14:09下载
- 积分：1
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20081209_Test_maus
Its project to move your mouse cursor on a vga monitor. it is very funny -)(Its project to move your mouse cursor on a vga monitor. it is very funny -))
- 2009-05-12 18:53:12下载
- 积分：1
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sd_models_verilog
测试过可用的SD仿真模型，VERILOG语言(SD card simulation modle, test OK)
- 2021-02-26 20:09:37下载
- 积分：1
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VHDL的应用：USB
VHDL的应用：USB-BLASTER的原理图-VHDL FOR USB-BLASTER
- 2022-04-23 08:50:27下载
- 积分：1
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Hardware Description Language VHDL of the frequency counter program can be used...
硬件描述语言VHDL的频率计程序,可用于做实验,或者初学者借鉴.-Hardware Description Language VHDL of the frequency counter program can be used for experiments, or the beginners learn.
- 2023-01-23 07:20:04下载
- 积分：1
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BT656_RGB
BT656转RGB的算法实现代码，使用VORILOG语言编写(BT656-->RGB, verilog)
- 2021-02-24 09:39:39下载
- 积分：1
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clk_div_4
说明： Verilog代码实现四分屏，在Vivado平台下实现的，可仿真(Verilog code realizes four screens, which can be simulated under vivado platform)
- 2020-12-21 20:39:08下载
- 积分：1
