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adder

于 2022-06-21 发布 文件大小:5.02 kB
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代码说明:

This the adder VHDL code, it contains input and output fild, also simulate file-adder

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  • 这是很全的标准库啊,不是1164.vhd,都是一些加,乘,除,平方等操作的包来的....
    这是很全的标准库啊,不是1164.vhd,都是一些加,乘,除,平方等操作的包来的.-This is the standard for the whole ah, not 1164.vhd are some increases, multiplication, addition, operational square packages to come.
    2022-06-21 05:49:57下载
    积分:1
  • verilog 我自己写得按单脉冲发生器,通过了综合和仿真,和频率可变的正弦波发生器,...
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    2022-04-19 00:17:00下载
    积分:1
  • this come from alter ,you can look and find it on line about USB
    this come from alter ,you can look and find it on line about USB
    2023-09-06 16:15:03下载
    积分:1
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    2020-07-03 07:00:02下载
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