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clk_div3
基于XIlinx ISE，用Verilog语言实现3分频电路，适合初学者(Based XIlinx ISE, Verilog language using the frequency dividing circuit 3, suitable for beginners)
- 2017-04-03 23:29:15下载
- 积分：1
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XILINXCPLD combine the simulation RS232 communication Verilog source
结合XILINXCPLD所做的模拟RS232通信verilog源程序-XILINXCPLD combine the simulation RS232 communication Verilog source
- 2022-01-28 06:03:56下载
- 积分：1
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sobel
Verilog代码实现Sobel算子，包括整个工程，仿真也有。。仿真表明该程序能实现Sobel 算子硬件实现(Verilog，Sobel Operator)
- 2011-05-10 21:11:21下载
- 积分：1
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source
ＦＰＧＡ与ＳＤＲＡＭ 的 ＶＨＤＬ 接口设计(ｔｈｅ interface of FPGA and SDRAM)
- 2012-03-28 22:17:19下载
- 积分：1
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- 2022-01-26 03:14:33下载
- 积分：1
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Complete-RAM
ram 64KB designed by haneesh in verilog
- 2011-07-15 00:57:01下载
- 积分：1
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ALOHA
this program is a simulation for Aloha
- 2012-11-13 11:38:10下载
- 积分：1
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基于ＦＰＧＡ，实现了移位除法的功能，程序接口简单，十分好用，已经验证。...
基于ＦＰＧＡ，实现了移位除法的功能，程序接口简单，十分好用，已经验证。-Based on the FPGA, to achieve the division of functional shift, the program interface is simple, very easy to use, has already been verified.
- 2022-10-14 07:10:02下载
- 积分：1
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本程序是用VHDL语言实现电子密码锁功能,整个系统分为三大模块,一为控制模块,二为键盘显示模块,三为处理模块...
本程序是用VHDL语言实现电子密码锁功能,整个系统分为三大模块,一为控制模块,二为键盘显示模块,三为处理模块-This procedure is a VHDL language electronic code lock function, the entire system is divided into three modules, one for the control module, two for the keyboard display module, three modules for the treatment
- 2022-05-08 19:29:46下载
- 积分：1
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NCO of the VHDL process is the use of nuclear
NCO的VHDL程序，是利用IP核生成的，超好的，快下吧-NCO of the VHDL process is the use of nuclear-generated IP, super good, fast, are you
- 2022-03-22 15:41:09下载
- 积分：1
