-
DE2 SOPC LCM
DE2 S O P C 用硬件语言 描述地 开发板上测试 CLM模块 实现视频传输-DE2 SOPC LCM
- 2022-07-01 11:31:51下载
- 积分:1
-
FIR低
fir低通滤波器 用于dspbuilder pll:25ns data 400khz sin 10.8khz-fir low-pass filter for dspbuilder pll: 25ns data 400khz sin 10.8khz
- 2023-05-01 00:45:03下载
- 积分:1
-
dp_xiliux the CPLD Verilog design experiments, 7 LED demo. code test.
dp_xiliux 的 CPLD Verilog设计实验,7个LED演示.代码测试通过. -dp_xiliux the CPLD Verilog design experiments, 7 LED demo. code test.
- 2023-03-22 17:40:04下载
- 积分:1
-
S03_基于ZYNQ的DMA与VDMA的应用开发
说明: VIVADO dma以及vdma 使用文档 基于ZYNQ 7020(vivado DMA&VDMA example text of zynq)
- 2020-06-17 11:40:02下载
- 积分:1
-
带load、clr等功能的寄存器
带load、clr等功能的寄存器-belt load, the function clr Register
- 2022-06-20 10:15:42下载
- 积分:1
-
txt_util
VHDL库,仿真时使用的,包括打印,类型转换等实用的操作(Practical operation VHDL library, using simulation, including print, type conversion, etc.)
- 2014-05-23 13:07:31下载
- 积分:1
-
在QuartusII运用AHDL语言,首先设计出PN发生器来产生一个11位的数据流在整个周期内有效数据有 =2047位;再设计状态机用来检测串行数据流中的序列。...
在QuartusII运用AHDL语言,首先设计出PN发生器来产生一个11位的数据流在整个周期内有效数据有 =2047位;再设计状态机用来检测串行数据流中的序列。运用两个个计数器分别对PN码计数以及序列出现的次数计数。改变PN码结构可以作为通用数列检测器-QuartusII use in AHDL language, the first PN generator designed to generate a data stream 11 throughout the cycle has an effective data = 2047 re-designing the state machine used to detect the serial data stream in sequence. The use of two counters were counting on the PN code, as well as counting the number of sequences occur. Changes in the structure of PN code series can be used as general-purpose detector
- 2023-03-11 09:20:03下载
- 积分:1
-
divisor
Time divisor vhdl code
- 2009-06-02 21:31:05下载
- 积分:1
-
《Verilog HDL 程序设计教程》2
《Verilog HDL 程序设计教程》2-"Verilog HDL Design Guide," 2
- 2022-03-04 04:35:38下载
- 积分:1
-
altera de2 开发板 vga lcd控制quatus 工程
altera de2 开发板 vga lcd控制quatus 工程-altera de2 board vga lcd control quatus works
- 2023-05-15 10:55:03下载
- 积分:1