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verilog实现的“BCD/七段译码器”。
verilog实现的“BCD/七段译码器”。-verilog implementation " BCD/Seven-Segment Decoder."
- 2022-12-23 05:15:02下载
- 积分：1
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OFDM_CP
ofdm系统的matlab实现，包括插入导频信号和循环前缀(Matlab implementation of ofdm system, including inserted pilot frequency signal and the cyclic prefix)
- 2013-05-29 10:10:23下载
- 积分：1
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zuixiangxide_NIOS_kaifajiaocheng
来自于NIOSII的那些事，该书详细地介绍了NIOSS的使用过程，非常适合初学者。(From the NIOSII those things, the book are detailed in this paper NIOSS use process, very suitable for beginners.
)
- 2011-12-13 11:33:57下载
- 积分：1
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PID-algorithm
PID算法控制点击速度，PWM脉宽调制方法(PID algorithm to control the motor
Speed)
- 2012-03-22 12:23:09下载
- 积分：1
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VHDL_biss
FPGA中针对Biss通讯协议解码VHDL语言源码(FPGA communication protocols against BiSS source decoder VHDL language)
- 2021-03-15 19:19:22下载
- 积分：1
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5
fpga paper function fff(fpga paper function)
- 2010-03-11 23:15:24下载
- 积分：1
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Image-Interpolation-Algorithm
文档包括双线性插值算法和最近邻域算法的详细介绍，以及算法的相关计算。(Documentation includes bilinear interpolation algorithm and the nearest neighbor algorithm which is described in detail, as well as algorithms related calculations.)
- 2020-06-30 21:40:01下载
- 积分：1
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PWM for control of motors
PWM for control of motors
- 2022-07-25 05:36:51下载
- 积分：1
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华为内部的FPGA设计培训教程，详细阐述了设计流程图、Verilog HDL设计、逻辑仿真、逻辑综合。对大家的学习一定有帮助的。...
华为内部的FPGA设计培训教程，详细阐述了设计流程图、Verilog HDL设计、逻辑仿真、逻辑综合。对大家的学习一定有帮助的。-Huawei within the FPGA design training tutorial, a detailed flow chart of the design, Verilog HDL design, logic simulation, logic synthesis. Study of the U.S. must have help.
- 2023-05-11 10:40:03下载
- 积分：1
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我用过的verilog hdl写的SDRAM core源程序,经过测试应用
我用过的verilog hdl写的SDRAM core源程序,经过测试应用-I used to write Verilog HDL source of SDRAM core, the test application
- 2022-01-23 10:44:34下载
- 积分：1
