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Writing-Testbenches-using-System-Verilog
writing testbench in system verilog
- 2011-12-11 06:02:47下载
- 积分：1
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shuzishizhong
这是基于verilog hdl的数字时钟源代码，能够实现时分秒的计时，可以手动进行调时与调分。(This is based on the digital clock verilog hdl source code, can be achieved when every minute of the time, you can adjust the time manually adjusting points.)
- 2013-12-10 22:21:55下载
- 积分：1
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fft_fpga_dit
Decimation-In-Time Fast Fourier Transform
I"ve tried to make the implementation simple and well documented.
I have not tried to make it efficient.
dit.v - Contains main module.
buffer.v - Contains a module for a single butterfly step.
generate_twiddlefactors.py - Contains function to generate a verilog file with twiddlefactors.
twiddlefactors_N.v.t - Template used to generate verilog file.
dut_dit.v - A wrapper around the "dit" module to allow verification with MyHDL.
qa_dit.py - A MyHDL test bench for verification.
Requires MyHDL, iverilog and numpy to be installed.
pyfft.py - Generates output of intermediate FFT stages. Useful for debugging.
- 2022-03-30 05:04:52下载
- 积分：1
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CRC
说明： 10G网络 CRC-32 CRC-64计算代码(10G Network CRC-32 CRC-64 Computing Code)
- 2020-06-22 19:20:01下载
- 积分：1
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generic_dpram
IT IS THE DP MEMORY MODULE. IT CONTROLS THE DP MEMORY
- 2013-09-30 19:03:40下载
- 积分：1
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gtx_interface_ip
高速串行设计FPGA-GTX IP设置生成，可动态配置速率2.4Gbps，1.2Gbps，0.6Gbps，自适应链接(High-speed serial design FPGA-GTX IP settings generated dynamically configurable rate of 2.4Gbps, 1.2Gbps, 0.6Gbps, adaptive link)
- 2016-09-22 09:48:00下载
- 积分：1
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LDPC-long40rate0.5-encode-and-decode
LDPC的短码，码长为40速率为0.5的LDPC码的设计，用的是QC矩阵，压缩文件为原码部分，工程太大传不上去。(LDPC short code, a code length of 40 rate of 0.5 LDPC code design, using a QC matrix, the compressed file is part of the original code, do not pass up the works too.)
- 2013-07-01 09:28:47下载
- 积分：1
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performance with rayleigh
说明： matlab bpsk with rayleigh performance expirement
- 2020-06-24 21:40:01下载
- 积分：1
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AVQR
单相的主动式电压质量控制器 对电压跌落进行了补偿(single-phase AVQR for power quility improvement)
- 2012-10-29 15:52:24下载
- 积分：1
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FPGAtraining
远立科技FPGA培训文档,关于GFP项目的一些细节，很好的！(Yuan established FPGA technology training documentation)
- 2011-01-11 13:52:10下载
- 积分：1
