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dac
说明： DA芯片输出控制 SPI协议 只写不读 FPGA用 verilog(DA-chip SPI protocol output control does not read write-only FPGA with verilog)
- 2011-03-16 19:04:33下载
- 积分：1
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EDA
EDA技术及其应用《序列信号发生器的设计》，包括源文件。(EDA technology and its applications " sequence signal generator design, including source files.)
- 2012-10-29 18:30:40下载
- 积分：1
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Some_classic_examples_of_VHDL_language_source_code
ＶＨＤＬ语言的一些经典实例源代码，包括状态机，时序电路，组合逻辑电路等(Some classic examples of VHDL language source code, including the state machine, sequential circuits, combinational logic circuits)
- 2010-07-11 12:50:06下载
- 积分：1
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cordic
16级流水线型cordic旋转代码以及测试文件，亲测好用(16-stage pipelined cordic rotation code and test files, pro-testing)
- 2019-03-09 08:59:01下载
- 积分：1
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fft，ifft verilog代码
快速傅立叶变换及反变换
快速傅立叶变换及反变换的verilog代码，altera官网提供，也可以从http://www.altera.com.cn/网址查找。做数字信号处理的同学可以看看。
- 2022-01-27 22:39:51下载
- 积分：1
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ASKMod
ASK调制信号的verilog VHL设计，在ise中实现了ASK信号的调制解调。(ASK modulation signal verilog VHL design, in ise to achieve the ASK signal modulation and demodulation.)
- 2017-04-17 10:46:19下载
- 积分：1
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8 位 CPU vhdl实现（含全部源代码）
说明： 这是8位CPU的CVDL代码。CPU 的主要功能是执行指令，控制完成计算机的各项操作，包括运算操作、传送操作、输入/输出操作等。作为模型计算机设计，将重点放在寄存器级，采取较简单的组成模式，以尽量简洁的设计帮助学生掌握CPU 的基本原理。 此次设计CPU就是为了了解CPU运行的原理，从而完成从指令系统到CPU的设计，并且通过仿真对CPU设计进行正确性评定。(The main function of CPU is to execute instructions, control and complete various operations of computer, including operation, transfer operation, input / output operation, etc. As a model computer design, it focuses on register level and adopts a simpler composition mode to help students master the basic principles of CPU with a concise design as far as possible. This design of CPU is to understand the principle of CPU operation, so as to complete the design from instruction system to CPU, and evaluate the correctness of CPU design through simulation.)
- 2020-12-09 15:49:20下载
- 积分：1
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Raster_Requ_Ctrl
电路四倍频算法，具有去毛刺，整形功能，方向及计数(Circuit quadruple frequency algorithm, with deburring, shaping function)
- 2020-06-20 01:00:02下载
- 积分：1
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ofdm_integration
整合的OFDM调制解调方法，matlab文件，modelsim仿真(Integration OFDM modulation and demodulation method, matlab file, modelsim simulation)
- 2012-09-03 17:13:35下载
- 积分：1
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shuzizhong3
数字钟VHDL软件设计，包含多种功能，报时，12,24切换，调时(The design of VHDL digital clock software, including a variety of functions, timer, 12,24 switch, adjustable)
- 2016-05-27 11:41:22下载
- 积分：1
