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pc_cfr_test_v3_1c
一个关于降低现代通信系统中高峰均比信号的matlab算法，对于研究数字预失真基于FPGA实现的有一定作用！(A modern communication system on the lower than the peak signal matlab algorithm for FPGA-based study of digital pre-distortion to achieve a certain effect!
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- 2011-07-07 22:01:17下载
- 积分：1
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RX_RS_DEC
OFDM系统新型RS编解码的verilogHDL设计，经测试误码率性能提高(OFDM system verilogHDL new RS codec design, improved bit error rate performance tested)
- 2020-12-31 10:59:00下载
- 积分：1
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67_ellipf
vhdl very good debug release vhdl very good debug release
- 2006-10-22 18:39:48下载
- 积分：1
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Fast_median_filter
说明： FPGA数字图像处理实现均值滤波，并且仿真将生成图片写出TXT格式以便使用MATLAB查看(Mean filter is realized by digital image processing in FPGA, and the generated image is written in TXT format for viewing with MATLAB.)
- 2019-06-01 21:23:25下载
- 积分：1
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can-lite-vhdl-master
CAN VHDL Code. Behavioral implementation of CAN bus interface.
- 2021-01-19 21:48:41下载
- 积分：1
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textiowrite
quartus ii 环境下，一个完整的利用TEXTIO仿真的源代码，包括读数据文件和输出数据到文件。(Under quartus ii environment, a complete simulation using TEXTIO source code, including reading data files and output data to a file.)
- 2014-02-03 23:56:30下载
- 积分：1
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digital-processing-with-FPGA
vhdl语言，国外教材，数字信号处理算法(vhdl language, foreign materials, digital signal processing algorithms)
- 2016-07-22 21:53:49下载
- 积分：1
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LED loop example
资源描述Xilinx FPGA板子实现LED 循环亮灯的例子，对初学者学习Verilog硬件描述语言非常有帮助！
- 2022-08-21 20:21:14下载
- 积分：1
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tongbu
使用VERILOG开发时钟同步算法，能够从数据信号中提取时钟信息，(Clock synchronization algorithm using VERILOG developed to extract the clock from the data signal information,)
- 2020-11-11 12:39:44下载
- 积分：1
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callback
This is code of UVM CALLBACK function.
- 2020-06-24 15:40:02下载
- 积分：1
