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binary_adder_subtractor
binary adder / subtracter in vhdl
- 2012-12-10 14:54:57下载
- 积分：1
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FFT_Module
接收机数字部分FFT模块的代码
包括verilog代码、
matlab仿真、
word文档
testbench
实现FFT(The code of the digital part FFT module of the receiver
Including Verilog, matlab simulation, testbench
Implementation of FFT)
- 2020-11-18 20:49:38下载
- 积分：1
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数字钟的实现 FPGA上运行 VHDL编写
数字钟的实现 FPGA上运行 VHDL编写-Digital clock running on the FPGA to achieve the preparation of VHDL
- 2023-08-20 09:25:06下载
- 积分：1
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Avalon_VGA_Controller
基于ALTERA AVALON BUS 的 VGA Controller 设计(ALTERA AVALON BUS VGA Controller )
- 2014-09-23 21:07:40下载
- 积分：1
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Microsoft-Word--(11)
信号源模块源程序,可以实现程序模块的实现，然后发生需要的程序(Source module source code, you can achieve the realization of the program modules, and the occurrence of the required procedures)
- 2014-12-30 11:12:32下载
- 积分：1
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craps
this is the source code we have been working on for our project using altera de2 board. the code can be run but some of it miss the end game module, while some doesn t have the complete vga code
- 2014-05-20 15:21:23下载
- 积分：1
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sdram
SDRAM驱动器，自己项目利用的，已经经过实际验证(sdram controller)
- 2010-01-28 14:13:35下载
- 积分：1
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LCD_1602
说明： 以ISE为开发环境，Verilog语言编写程序。功能：FPGA控制 LCD_1602动态显示秒表(In the development environment of ISE, Verilog language is used to write programs. Function: LCD_1602 dynamic display stopwatch controlled by FPGA)
- 2020-06-20 00:00:02下载
- 积分：1
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用VHDL语言编写的代码，以供大家学习和交流，方便大家学习！...
用VHDL语言编写的代码，以供大家学习和交流，方便大家学习！-prepared using VHDL code for all to study and exchange to facilitate learning!
- 2023-01-23 12:20:04下载
- 积分：1
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PC
说明： Verilog HDL语言编写的32位程序计数器（PC）完整工程及相应仿真，QuartusII7.2下编译通过可正常使用。(Complete engineering and simulation of Verilog HDL language of the 32-bit program counter (PC), QuartusII7.2 compiled through normal use.)
- 2012-09-06 09:07:47下载
- 积分：1
