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一个同步有限状态机（FSM）的设计是一个数字的共同任务…
Designing a synchronous finite state machine (FSM) is a common task for a digital
logic engineer. This paper discusses a variety of issues regarding FSM design using
Synopsys Design Compiler. Verilog and VHDL coding styles are presented, and
different methodologies are compared using real-world examples.
- 2022-01-26 02:12:10下载
- 积分：1
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10_rom_test
说明： 介绍如何使用 FPGA 内部的 ROM 以及程序对该 ROM 的数据读操作。(This paper introduces how to use the ROM inside the FPGA and how to read the data of the ROM by the program.)
- 2019-03-30 16:39:57下载
- 积分：1
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pex8311代码实现
pex8311代码实现 altera的fpga 代码编程 实现本地读写 pex8311_test
- 2022-01-28 06:56:26下载
- 积分：1
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alu
this is the vhdl code for the arithmetic logic unit.enjoy!
- 2013-08-22 18:51:35下载
- 积分：1
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1
说明： matlab code for JTAG cable checking
- 2014-02-04 19:27:39下载
- 积分：1
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Over_Current_Relay_Co_ordination
try this for pq improvmnett
- 2012-11-17 05:40:30下载
- 积分：1
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I2C-code
I2C总线协议 Verilog源代码.试过，没有错误！可以直接使用(I2C bus protocol Verilog source code. Tried, no errors! Can be used directly)
- 2013-06-03 10:54:17下载
- 积分：1
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fpgaConfig_V1_2_SFLASH_20090507a
自己写的一个使用单片机配置FPGA的下位机C代码，使用一个C8051F330,外置SPI FLASH,通过串口可将程序写入FLASH,上电时自动加载到FPGA完成配置。(Wrote it myself, using a microcontroller to configure FPGA code for the next bit plane C, using a C8051F330, external SPI FLASH, the program is written through the serial port can be FLASH, power-on automatically loaded into the FPGA to complete the configuration.)
- 2021-02-16 07:29:47下载
- 积分：1
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lanqiu24s8
篮球24s计时。计时器递减计数到零时，数码显示器显示‘0’并停止，同时发出报警信号(basketball 24 seconds)
- 2012-06-11 16:04:01下载
- 积分：1
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ZBT-sram控制器VHDL.doc
----------------------------------------------------------------------------------
-- Company: VISENGI S.L. (www.visengi.com) - URJC
FRAV Group (www.frav.es)
-- Engineer: Victor Lopez Lorenzo (victor.lopez (at)
visengi (dot) com)
--
-- Create Date: 12:39:50 06-Oct-2008
-- Pr
- 2022-03-02 23:54:43下载
- 积分：1
