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ADS8509
FPGA驱动高输入电压范围的ADS8509芯片，采样范围广，适合前端大信号处理(FPGA drive a high input voltage range ADS8509 chip, sampling a wide range, suitable for large front-end signal processing)
- 2015-08-10 22:03:59下载
- 积分：1
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55593402DDS_vhdl
DDS分频实现，全部代码的完整过程，包括截图等(DDS divider to achieve the complete process of all the code)
- 2013-05-15 16:49:55下载
- 积分：1
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20190717 - Copy
this describes building spi block on verilog hdl and programming them on an fpga device
- 2020-06-21 21:40:02下载
- 积分：1
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A counter that starts from 0 and increments mod 16 on each rising edge of the cl...
A counter that starts from 0 and increments mod 16 on each rising edge of the clock
- 2022-09-16 15:40:03下载
- 积分：1
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shuzishizhong
基于DE2-115开发板设计的一个数字钟，能进行正常的小时、分、秒计时功能，并分别由开发板上面的数码管显示秒（60s）、分（60min）、小时（24hours）的时间。并具有手动调整时间的功能(DE2-115 board design based on a digital clock, and enables the normal hours, minutes, seconds chronograph function, and were above the development board digital display seconds (60s), points (60min), hours (24hours) time . And has a function to manually adjust the time)
- 2020-11-01 11:39:54下载
- 积分：1
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VHDL digital system design and engineering practice 4, including the principles,...
VHDL数字系统设计和工程实践5，包含原理，真值表和原理图，以及VHDL源代码.-VHDL digital system design and engineering practice 4, including the principles, truth table and schematic, as well as VHDL source code.
- 2022-08-11 13:48:51下载
- 积分：1
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cmos-Digital-design
The deep lecture notes for basic digital system for cmos design
- 2012-07-29 17:51:26下载
- 积分：1
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FIR低
fir低通滤波器 用于dspbuilder pll：25ns data 400khz sin 10.8khz-fir low-pass filter for dspbuilder pll: 25ns data 400khz sin 10.8khz
- 2023-05-01 00:45:03下载
- 积分：1
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vhdl
code for fft non synthesisable in xilinx ise
- 2013-09-30 13:16:13下载
- 积分：1
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e2
说明： Any change to the value of Mresults in immediate and phase-continuous changes in the output frequency
- 2014-02-23 02:42:47下载
- 积分：1
