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huawei
华为内部资料，包括verilog电路设计，硬件工程师手册，verilog约束，synplify使用指南等。内容较全面。(Huawei internal information, including verilog circuit design, hardware engineers manual, verilog constraints, synplify use guides. Content more comprehensive.)
- 2015-07-11 20:08:52下载
- 积分：1
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Verilog ADPLL文件与测试
verilog ADPLL file with testbench
- 2022-04-18 06:08:09下载
- 积分：1
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8.8-URAT-VHDL
URAT VHDL程序与仿真 URAT the VHDL program and Simulation
(URAT the VHDL program and Simulation
)
- 2012-04-09 20:53:45下载
- 积分：1
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clk
sin波形发生图形，应用智能老师款到即发了快速打击 (sin waveform generation graphics application smart teacher paragraph to that made a rapid strike)
- 2013-02-24 15:46:58下载
- 积分：1
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基于fpga的交织编码器设计，主要讲叙如何在fpga上实现交织编码器。...
基于fpga的交织编码器设计，主要讲叙如何在fpga上实现交织编码器。-something about turbo。
- 2023-02-09 02:35:04下载
- 积分：1
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6通道正弦波发生器，产生频率，相位，幅值都可调的正弦波形...
6通道正弦波发生器，产生频率，相位，幅值都可调的正弦波形-6-channel sine wave generator, resulting in frequency, phase, amplitude of the sinusoidal waveform are adjustable
- 2022-10-22 04:00:03下载
- 积分：1
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hdlc
HDLC通信协议，FPGA实现，包含源文件和仿真测试文件。(HDLC comunication)
- 2014-08-28 21:37:31下载
- 积分：1
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基于FPGA的CPU核及其虚拟平台的设计与实现
基于FPGA的CPU核及其虚拟平台的设计与实现-FPGA-based CPU core and its virtual platform design and implementation of
- 2022-08-08 02:35:45下载
- 积分：1
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RAYLEIGH
matlab 编的瑞利信道仿真源码，对研究信道很有用(hgajdjkjhakhdkhakjlkjlka)
- 2010-01-17 20:47:43下载
- 积分：1
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根据音乐发生的机理，将复杂可编程逻辑器件作为发生音乐的核心器件，用高速集成电路硬件描述语言编程描述发生的音乐乐谱，配合周边硬件电路，由电声转换发声器接收信号，从...
根据音乐发生的机理，将复杂可编程逻辑器件作为发生音乐的核心器件，用高速集成电路硬件描述语言编程描述发生的音乐乐谱，配合周边硬件电路，由电声转换发声器接收信号，从而发出音乐声，实验表明，采用该方法设计的音乐发生器成本低、修改方便-Music took place in accordance with the mechanism of complex programmable logic device, as occurred in the core of music devices, with high-speed integrated circuit hardware description language to describe the occurrence of music notation, with the peripheral hardware circuits, electro-acoustic conversion by the audible signal device to receive signals, which issued music, experiments show that this method of music generator design and low cost, easy to amend
- 2023-06-27 23:25:04下载
- 积分：1
