登录
首页 » VHDL » 16位元浮点数CPU,可作运算,以VHDL编写

16位元浮点数CPU,可作运算,以VHDL编写

于 2022-05-17 发布 文件大小:2.28 kB
0 116
下载积分: 2 下载次数: 1

代码说明:

16位元浮点数CPU,可作运算,以VHDL编写-16-bit floating point CPU, can be used for computing in order to prepare VHDL

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • keyboard
    用FPGA单片机软核实现键盘扫描,键盘为4X4矩阵键盘,输入相应键值,用数码管显示-keyboard
    2022-05-20 15:47:09下载
    积分:1
  • 16QAM
    QAM调制模块,可用于Quartus仿真与fpga硬件实现。(QAM Modulation Mode, can be used for Quartus simulation and FPGA.)
    2013-12-27 10:01:48下载
    积分:1
  • SIREN
    An Alarm Project Writen in VHDL for FPGA Devices
    2010-10-01 16:37:48下载
    积分:1
  • AD9250 204b Verilog源码
    说明:  AD9250是一款双通道14位ADC,最高采样速率250 MSPS,JESD204B Subclass 0或Subclass 1编码串行数字输出(The ad9250 is a dual channel 14 bit ADC with a maximum sampling rate of 250 MSPs and jesd204b sub class 0 or sub class 1 coded serial digital output)
    2021-04-14 11:01:55下载
    积分:1
  • game
    反应速度测试小游戏,最小外设cpld游戏,带设计说明书(Reaction speed test games, the minimum peripheral cpld game, with design specifications)
    2010-05-14 18:42:57下载
    积分:1
  • New-Folder
    to learn bout development of vhdl code
    2014-03-15 16:21:38下载
    积分:1
  • xilinx_usb_drivers_win10_x64
    win10的xilinx usb驱动,较新版本(Xilinx USB driver for win10, newer version)
    2021-03-11 17:09:26下载
    积分:1
  • DDS
    DDS的VHDL源代码,是数字QPSK调制解调中的重要组成部分。(DDS of the VHDL source code, the number of QPSK modulation and demodulation is an important part.)
    2007-12-11 16:26:33下载
    积分:1
  • vhdl对dds的原理设计,由衷要得论文价值。不后悔
    vhdl对dds的原理设计,由衷要得论文价值。不后悔-right dds VHDL design principle, we sincerely value of fine papers. No regrets
    2022-07-26 10:48:53下载
    积分:1
  • tlc5615
    TLC5615串行DA的驱动接口,采用verilog编程(TLC5615 driver DA serial interface using verilog programming)
    2009-04-27 11:59:22下载
    积分:1
  • 696518资源总数
  • 106174会员总数
  • 31今日下载