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429recive
实现FPGA接收429板卡发送的信号，并根据数据最后两位点亮相应的LED。(FPGA to achieve the 429 board to receive the signal sent, and according to the data of the last two of the corresponding LED.)
- 2015-11-26 11:18:19下载
- 积分：1
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FIFO
fifi asyncronous and syncronus
- 2012-04-30 02:31:24下载
- 积分：1
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CCDDRIVE(TCD1206UD)
关于一款线阵CCD TCD1206UD 的驱动设计，波形符合工作要求(On how the system in SOPC using HDL language development from a custom IP core)
- 2020-11-14 09:19:42下载
- 积分：1
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shuzihongdianlu
数字钟电路的实现，可以24小时计时，可调整时间！(Digital clock circuit implementation, a 24-hour timer, adjustable time!)
- 2013-08-18 14:49:14下载
- 积分：1
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实现在屏幕上显示绿色和红色相间的水平条纹
实现在屏幕上显示绿色和红色相间的水平条纹。其中，vga_640x480模块将产生行同步信号hsyn和场同步信号 vsync; vga_stripes模块将产生red、green和blue三个输出。(The horizontal stripes of green and red are displayed on the screen. Among them, vga_640x480 module will produce line synchronization signal Hsyn and field synchronization signal vsync; vga_stripes module will produce red, green and blue three outputs.)
- 2020-06-24 02:00:02下载
- 积分：1
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fft-matlab
FFT的MATLAB实现。非常完整的实现FFT过程，速度很快。(The FFT in MATLAB. Contains more than one source, the FFT process. Learning Reference essential)
- 2012-10-27 16:07:24下载
- 积分：1
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IEEE 802.3 Cyclic Redundancy Check参考设计，xilinx提供
IEEE 802.3 Cyclic Redundancy Check参考设计，xilinx提供-IEEE 802.3 Cyclic Redundancy Check reference design for Xilinx
- 2023-02-15 07:55:03下载
- 积分：1
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电子闹钟：基于fpga的电子闹钟设计，采用模块化方式
电子闹钟：基于fpga的电子闹钟设计，采用模块化方式-Electronic alarm: FPGA-based electronic alarm clock design, modular approach
- 2022-02-06 03:24:59下载
- 积分：1
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VHDL_modelling_guidelines是vhdl建模开发的指导资料
VHDL_modelling_guidelines是vhdl建模开发的指导资料-VHDL modeling VHDL_modelling_guidelines is guiding the development of information
- 2022-03-12 23:37:10下载
- 积分：1
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divid5_VERILOG
VERILOG实现无分频时钟，包括测试文件，经过验证可用(VERILOG is no difference between the frequency of the clock implementation, including test papers, can be used after authentication)
- 2009-03-30 15:11:30下载
- 积分：1
