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FPGA
spwm dcac逆变 fpga与单片机一起作用(sdad)
- 2010-08-12 18:20:08下载
- 积分:1
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verilog_DATA_displays
使用verilog语言,滚动显示“verilog”字符串程序代码及相关说明(Using verilog language, scrolling display " verilog" string code and instructions)
- 2014-01-16 10:49:55下载
- 积分:1
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用verilog写的CORDIC算法实现,很适合做超越函数的运算。通常用于实现正弦乘法,或者坐标变换。...
用verilog写的CORDIC算法实现,很适合做超越函数的运算。通常用于实现正弦乘法,或者坐标变换。-The cordic arithmetic implemented by verilog is adapted to exceed function.It is usually used to implement sine multiplication or coordinate tuansform.
- 2022-05-25 08:44:55下载
- 积分:1
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shuzizhongsheji
有用的数字钟设计文档,有秒表、闹钟等模块,希望对大家有用!(JUST LEARN FROM IT!!ENJOY!)
- 2013-07-18 11:02:24下载
- 积分:1
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用VHDL写的源代码程序,包涵三人表决器,七人表决器,全加器以及模24,模60的计数器,都是单文件的,由于程序小又多,所以集中在一起,供新学习VHDL语言的朋友...
用VHDL写的源代码程序,包涵三人表决器,七人表决器,全加器以及模24,模60的计数器,都是单文件的,由于程序小又多,所以集中在一起,供新学习VHDL语言的朋友们参考。-With VHDL source code written procedures, includes three of the voting machine, vote on seven people, and full adder, as well as modulus 24, modulus 60 counters, are single-file, as many small procedures, so together for the new Learning VHDL Language Reference friends.
- 2022-02-02 08:32:12下载
- 积分:1
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Variable Reduction Testbench通过对变量进行相关性分析来实现减少变量的目的。...
Variable Reduction Testbench通过对变量进行相关性分析来实现减少变量的目的。-Variable Reduction Testbench is a MATLAB module that allows the application of several methods for variable reduction based on correlation analysis
- 2022-03-21 18:04:20下载
- 积分:1
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NN-using-FPGA
thesis about design and implementation neural network using FPGA
- 2013-12-29 16:23:52下载
- 积分:1
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chuanganqi
传感信号无线数字传输系统的设计与实现.kdh(err)
- 2008-04-22 14:54:02下载
- 积分:1
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系统设计
说明: 基于无源蜂鸣器和矩阵按键的电子琴系统设计(design of Electronic Piano System Based on Passive Buzzer and Matrix Key)
- 2020-06-21 01:20:08下载
- 积分:1
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数控分频的一个工程
数控分频的一个工程---包括vhdl源程序和编译后产生的相关文件-CNC dividing frequency of a project- including VHDL source code and compile the relevant documents after
- 2022-05-22 23:30:57下载
- 积分:1