-
MAX2769配置源码_配置参数经过实际工程考验
对常用的射频端下变频的MAX2769芯片进行GPSL1频点配置,实测有效,该配置参数是经过实际工程验证的,现在也应用于实际项目中
- 2023-09-04 07:35:03下载
- 积分:1
-
sdram-control-verilog
SDRAM控制器源码,内含完整的控制器verilog源代码和测试代码,超值哈。(This readme file for the SDR SDRAM Controller includes information that was not
incorporated into the SDR SDRAM Controller White Paper v1.1.)
- 2009-12-11 15:01:46下载
- 积分:1
-
M_SSB_100
由乘法器组成 单边带信号产生的 仿真源代码 msm (Composed of single sideband signal by the multiplier generated simulation source code msm)
- 2007-07-25 14:59:29下载
- 积分:1
-
FPGA_AD7606
FPGA 与ad70676之间用并口通信 八个通道采集到的电压用串口打印出来(Parallel communication between FPGA and ad70676, the voltage collected by eight channels is printed out with serial port)
- 2017-10-27 09:17:15下载
- 积分:1
-
m_ca7
verilog编写的基于CA算法的m序列发生器,其中验证了多种CA系数来实现m序列。(CA-based algorithm written in verilog m-sequence generator, which verify the CA factor to achieve a variety of m-sequence.)
- 2011-10-26 14:33:59下载
- 积分:1
-
top
脉冲多普勒雷达回波信号相干积累的VHDL源程序(pulse Doppler radar echo signal coherent accumulation of VHDL source)
- 2021-04-22 20:28:48下载
- 积分:1
-
I2S_2
that file is different I2S example
- 2014-11-27 06:39:52下载
- 积分:1
-
三态总线 GPIO
(1) 与微处理器可编程三态总线接口 GPIO (通用目的输入和输出端口)(2) 总线接口:1.addr_reg: 地址总线2.rd_n_reg、 wr_n_reg、 cs_n_reg: 控制总线3.数据: 三态数据总线(3) 内部寄存器:
- 2022-02-05 04:28:07下载
- 积分:1
-
8_BUS
BUS documentation and map reffereces
- 2020-06-25 19:40:02下载
- 积分:1
-
FPGA实现百兆MAC发送接收
该部分实现了百兆MAC的数据的收发功能,可直接连接MII接口的PHY芯片,进行通信,设计是基于国半的DP83849双口PHY进行开发,并进行过大量实例测试;应用中有问题可随时联系
- 2023-08-19 16:00:03下载
- 积分:1