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this come from alter ,you can look and find it on line.
this come from alter ,you can look and find it on line.
- 2022-12-12 10:20:03下载
- 积分:1
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UC1608-24064
UC1608 24064驱动 COG LCD驱动程序(UC1608 24064)
- 2011-09-09 08:24:24下载
- 积分:1
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8B10B
以太网PHY层中的组成部分 8B10B编码器(Part of the Ethernet PHY layer in 8B10B encoder
)
- 2021-01-27 09:18:42下载
- 积分:1
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dp_xiliux the CPLD Verilog design experiments, clock demo. code test.
dp_xiliux 的 CPLD Verilog设计实验,时钟演示.代码测试通过. -dp_xiliux the CPLD Verilog design experiments, clock demo. code test.
- 2022-12-25 17:55:03下载
- 积分:1
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shift_reg
Shift reg in vhdl, a first example to start
- 2011-03-27 10:35:25下载
- 积分:1
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Verilog--Fourth-Edition
FPGA开发必备工具书,适合初学者。语法、范例讲的都很详细,是一部不错的工具书。(Verilog hardware description language Fourth Edition)
- 2015-09-30 12:34:50下载
- 积分:1
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Vhdl实现计算exp功能 在apex20k上经过验证
Vhdl实现计算exp功能 在apex20k上经过验证-Vhdl achieve in terms exp function on proven apex20k
- 2022-07-21 03:19:31下载
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vlog_flash_20090712.tar
说明: NAND FLASH的多个仿真模型,可以用于接口设计的测试(NAND FLASH multiple simulation model that can be used for the test interface design)
- 2009-08-05 21:14:07下载
- 积分:1
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CLZ32
针对32位MIPS微处理器中CLZ指令(对单个字高位连零进行计数)的实现电路,使用了类似于超前进位的逻辑结构。包含测试文档,以及Design
Compile所用的环境和脚本。(The CLZ instruction counts the number of leading zeros in a word. The 32-bit word in the GPR rs is scanned from most-significant to least-significant bit.The number of leading zeros is counted and the result is written to the GPR rd. If
all 32 bits are cleared in the GPR rs, the result written to the GPR rd is 32. )
- 2021-03-31 19:39:08下载
- 积分:1
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verilog2000更新部分,请对照前一个标准。加入了一些新的支持
verilog2000更新部分,请对照前一个标准。加入了一些新的支持-verilog2000 update, a former control standards. The inclusion of some new support
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