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DE2_PS2_Example
PS2 Module for Altera DE2
- 2017-06-20 21:04:32下载
- 积分：1
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5.c
; for 16-bit app support
[386Enh]
woafont=dosapp.fon
EGA80WOA.FON=EGA80WOA.FON
EGA40WOA.FON=EGA40WOA.FON
CGA80WOA.FON=CGA80WOA.FON
CGA40WOA.FON=CGA40WOA.FON
- 2017-11-07 04:17:08下载
- 积分：1
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用VHDL写的
用vhdl写的-using VHDL write
- 2022-03-16 07:17:41下载
- 积分：1
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newlin-pwm
VHDL 源码模块，可以实现最经典原PWM，可以用于电源，电机的控制()
- 2020-11-26 10:09:31下载
- 积分：1
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frequency
数字频率计，测量范围0-1GHZ,测周测频自动转换，精度极高，花了很长时间，不过还是有一点点小问题，有待改进.(Digital frequency meter, range 0-1GHZ, automatic conversion measured weekly frequency measurement, high precision, took a long time, but still a little small problems to be improved.)
- 2011-08-11 00:51:18下载
- 积分：1
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第七次课--视频图像DCT处理及水印嵌入
熟悉IIC协议总线协议，采用IIC总线对图像采集传感器寄存器进行配置，并转换为RGB565格式。
利用异步FIFO完成从摄像头输出端到SDRAM 和SDRAM 到VGA 接口各跨时钟域信号的传输和处理。
利用 SDRAM 接口模块的设计，实现了刷新、读写等操作；为提高SDRAM 的读写带宽，均采用突发连续读写数据方式；并采用乒乓操作实现 CMOS 摄像头与VGA的帧率匹配。
利用双线性插值方法实现对图像640×480到1024×768的放大操作。
完成VGA显示接口设计。(Familiar with IIC protocol bus protocol, IIC bus is used to configure the register of image acquisition sensor and convert it into RGB565 format.
Asynchronous FIFO is used to transmit and process signals across clock domain from camera output to SDRAM and SDRAM to VGA interface.
With the design of SDRAM interface module, refresh, read and write operations are realized. In order to improve the read and write bandwidth of SDRAM, burst continuous read and write data mode is adopted, and table tennis operation is used to achieve frame rate matching between CMOS camera and VGA.
The bilinear interpolation method is used to enlarge the image from 640*480 to 1024*768.
Complete the VGA display interface design.)
- 2020-06-25 04:00:02下载
- 积分：1
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FPGA Verilog HDL模拟IIC通讯接口
FPGA Verilog HDL模拟IIC通讯接口-FPGA Verilog HDL IIC Interface
- 2023-04-25 13:55:03下载
- 积分：1
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8051的Verilog
8051的Verilog-Verilog OF 8051
- 2022-06-15 04:13:18下载
- 积分：1
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bit
// Data port, granularity 8
// -*- Mode: Verilog -*-
// Filename : wb_master.v
// Description : Wishbone Master Behavorial
// Author : Winefred Washington
// Created On : 2002 12 24
// Last Modified By: .
// Last Modified On: .
// Update Count : 0
// Status : Unknown, Use with caution!
// Description Specification
// General Description: 8, 16, 32-bit WISHBONE Master
// Supported cycles: MASTER, READ/WRITE
// MASTER, BLOCK READ/WRITE
// MASTER, RMW
// Data port, size: 8, 16, 32-bit
// Data port, granularity 8-bit
// Data port, Max. operand size 32-bit
// Data transfer ordering: little endian
// Data transfer sequencing: undefined-//-*- Mode: Verilog-*-
// Filename : wb_master.v
// Description : Wishbone Master Behavorial
// Author : Winefred Washington
// Created On : 2002 12 24
// Last Modified By: .
// Last Modified On: .
// Update Count : 0
// Status : Unknown, Use with caution!
// Description Specification
// General Description: 8, 16, 32-bit WISH
- 2023-03-16 01:05:04下载
- 积分：1
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音频信号分析仪的FPGA源码
音频信号先经过由运放和电阻组成的50Ohm阻抗匹配电路以满足输入阻抗50 Ohm的系统要求，这样方便信号功率的计算。为了保证所处理的信号被不失真的采样，信号还要通过截止频率为10Khz的抗混叠低通滤波器。最后为了AD能正确的采样，信号还要通过信号抬高电路。
经过12位A/D转换芯片MAX144转换后的数字信号经由基于FPGA的NIOSII处理器进行FFT变换和处理，分析各个频率点的功率值，并将这些值显示在LCD上。
该源代码就是fft变换的源代码
- 2023-07-28 02:35:05下载
- 积分：1
