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pingpong
用Verilog代码实现的乒乓操作,用Verilog代码实现的乒乓操作(Verilog pingpong)
- 2016-01-15 17:35:06下载
- 积分:1
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9_ImageMorphologic
基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,图像形态学部分,腐蚀,膨胀,细化算法(System Generator based image processing engineering, multimedia processing FPGA implementation source code, image morphology section, corrosion, swelling, thinning algorithm)
- 2020-10-23 17:17:22下载
- 积分:1
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Commonly used phase
常用的锁相环技术,此程序是我在设计高频电路中运用的,具体见程序,经调试无问题-Commonly used phase-locked loop technology, this program is in the design I used in high-frequency circuits, see the specific procedures, no problem by debugging
- 2022-10-15 08:30:03下载
- 积分:1
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Signed-Arithmetic-in-Verilog-2001
有符号数的完整讲义和例子Verilog 2001(Signed Arithmetic in Verilog 2001, paper with examples)
- 2011-01-18 17:15:09下载
- 积分:1
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M序列?¨
生成一个M伪随机序列码,在ISE平台上可跑通(Generate an M Pseudo-Random Sequence Code which runs on ISE platform)
- 2019-05-05 15:54:38下载
- 积分:1
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VHDL-ELEVATOR-CONTORLLER-DESIGN
VHDL电梯控制器程序设计与仿真,内含原理图和VHDL源码,有助于学习VHFL(VHDL u7535 u68AF u63A7 u5236 u5668 u7A0B u5E8F u8BBE u8BA1 u4E0E u4EFF u771F)
- 2017-05-06 15:35:16下载
- 积分:1
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cic_4_dec
实现4倍抽取的CIC抽取滤波器模块的Verilog实现,在对数据进行抽取之前,首先进行滤波(Extracted 4 times realize CIC decimation filter module Verilog realize that in the data collected before the first filter)
- 2008-07-08 16:23:03下载
- 积分:1
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EDK_Tutorial_1
EDK tutorial 1 ----------------
- 2013-04-04 10:18:46下载
- 积分:1
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曼彻斯特编码技术用电压的变化表示0和1。规定在每个码元中间发生跳变。高→ 低的跳变表示0,低→ 高的跳变表示为1。每个码元中间都要发生跳变,接收端可将此变化提取...
曼彻斯特编码技术用电压的变化表示0和1。规定在每个码元中间发生跳变。高→ 低的跳变表示0,低→ 高的跳变表示为1。每个码元中间都要发生跳变,接收端可将此变化提取出来作为同步信号,使接收端的时钟与发送设备的时钟保持一致-Manchester coding techniques that use voltage changes in 0 and 1. Provisions in the middle of each symbol hopping happen. High → low hopping express 0, low → high jump for the express one. Symbol between each transition must happen, this change in the receiver can be extracted as a synchronization signal to the receiving end of the clock and send the equipment to maintain the same clock
- 2023-06-17 15:30:03下载
- 积分:1
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用CPLD驱动扬声器实现音乐的播放,程序是用VERILOG写的,
用CPLD驱动扬声器实现音乐的播放,程序是用VERILOG写的,-CPLD driver speakers with music player, the program is written in VERILOG,
- 2022-03-20 12:37:01下载
- 积分:1