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CPLD_DEMO_OK
可以给VHDL初学者看的实例，全部经过验证(VHDL beginners can see examples of all the proven)
- 2011-01-12 21:09:45下载
- 积分：1
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QAM_verilog
基于FPGA的16QAM，用verilog编写，其中DDS为自己编写，含设计文件和testbench。已通过moldesim软件仿真。 (FPGA-based 16QAM, with verilog writing, including DDS for their preparation, including design files and testbench. Simulation software has been through moldesim.)
- 2021-02-22 18:29:41下载
- 积分：1
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myfir
verilog编写的16阶升余弦滤波器 采用直接型结构实现 对方波进行滤波 输出波形 含testbench文件(order raised cosine filter verilog written 16 direct-type structure to achieve the other wave filtering the output waveform containing testbench file)
- 2020-10-05 16:47:44下载
- 积分：1
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WCDMA_DPD
WCDMA数字直放站中数字预失真研究及其FPGA实现(WCDMA Digital Repeater digital pre-distortion and its FPGA implementation)
- 2011-10-16 19:24:50下载
- 积分：1
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讲解快速傅里叶变换
讲解快速傅里叶变换--FFT快速算法的文章。-On Fast Fourier Transform- FFT fast algorithm for the article.
- 2022-06-01 02:12:26下载
- 积分：1
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TCL2543
基于FPGA的TLC2543控制器,采用状态进行控制ADC进行转换(The TLC2543 controller based on FPGA, using state control of ADC conversion)
- 2020-11-18 15:59:39下载
- 积分：1
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PSK
实现psk调制解调，vhdl代码，仿真文件也有(psk shixian tiaozhiyujietiao)
- 2013-04-10 14:24:53下载
- 积分：1
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ram32b
VHDL code for 32 byte RAM
- 2009-06-04 19:50:35下载
- 积分：1
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e2
Any change to the value of Mresults in immediate and phase-continuous changes in the output frequency
- 2014-02-23 02:42:47下载
- 积分：1
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NEW
Verilog投币式手机充电仪
清华大学数字电子技术基础课程EDA大作业。刚上电数码管全灭，按开始键后，数码管显示全为0。输入一定数额，数码管显示该数额的两倍对应的时间，按确认后开始倒计时。输入数额最多为20。若10秒没有按键，数码管全灭。(Verilog coin operated cell phone charger
EDA major homework of digital electronic technology foundation course, Tsinghua University. Just put on the digital tube completely extinguished, press the start button, the digital tube display is 0. Enter a certain amount, the digital tube shows the amount of double the corresponding time, according to the confirmation began countdown. The maximum amount of input is 20. If there is no button in 10 seconds, the digital tube will die out.)
- 2020-12-10 16:29:20下载
- 积分：1
