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eetop.cn_dds
基于verilog的DDS设计,内附代码,仿真环境等说明(the DDS design based on verilog)
- 2015-07-14 08:20:51下载
- 积分：1
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mult_16
用verilog实现对三个16位数进行相加乘法器(Three 16-digit sum of the multiplier Verilog)
- 2021-01-03 10:28:55下载
- 积分：1
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《Verilog HDL 程序设计教程》6
《Verilog HDL 程序设计教程》6-"Verilog HDL Design Guide" 6
- 2022-02-21 13:38:55下载
- 积分：1
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In the Altera chip 2C35F672 platform FFT procedures DSPBuilder5.0, generated Ver...
在Altera芯片2C35F672平台上的FFT程序，采用DSPBuilder5.0，生成Verilog文件。开发环境：QuartusII5.0。-In the Altera chip 2C35F672 platform FFT procedures DSPBuilder5.0, generated Verilog file. Development Environment: QuartusII5.0.
- 2022-03-16 05:08:13下载
- 积分：1
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histogram_new
Verilog语言描述，统计图片的像素值直方图(Verilog，Pictures of the pixel value histogram statistics)
- 2021-03-04 17:39:31下载
- 积分：1
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count4
这是一个基于Quartus2 开发环境的4输入加法器( 4adder basic on Quartus2)
- 2013-08-04 09:45:07下载
- 积分：1
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ecc
说明： This paper analyzes the cryptography scheme of the Trust Platform Model(TPM). The focus of the discussion would be the comparison of elliptic curve cryptography and the nowadays widely used 2048-bit RSA in evaluating which would be better suited to be used on TPM. A TPM implementation scheme based on ECC is proposed, which includes encryption and decryption schemes, signature and verification scheme, key agreement scheme. Corresponding examples of TPM commands would also be given.
- 2019-06-13 14:53:45下载
- 积分：1
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rom_fft
采用xilinx的ROMIP核产生类似正弦信号，经过FFt后可以观察结果(Using the xilinx ROMIP nuclear generating similar sinusoidal signal can be observed through the results after FFt)
- 2013-09-14 20:59:03下载
- 积分：1
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简易数字信号分析仪（眼图）
采用VHDL语言编写，此题为全国大学生电子设计竞赛题目，产生一个伪随机信号，并用时钟提取模块提取时钟，最终能在示波器上获得眼图，验证实验结果。此程序已经经过本人亲自验证，完全可用，可用于电赛培训之中。
- 2022-07-22 14:59:00下载
- 积分：1
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traffic_lights
用Verilog实现的交通信号灯控制，主干道和支路通行的时间不相等(Using Verilog implementation of traffic signal control, the trunk road and the slip is not the same passage of time)
- 2009-03-28 18:31:31下载
- 积分：1
