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DE2_115_CAMERA
实现DE2_115开发板上配套的500万像素cmos摄像头捕捉到的画面显示在VGA上(DE2_115 development board supporting 5,000,000 pixels cmos camera to capture the screen display in VGA)
- 2020-07-09 19:08:55下载
- 积分:1
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fjq1
介绍了在数字语音通信中, 利用在系统可编程技术和复杂可编程逻辑器件CPLD, 实现了数字语音的复接和分接
对于其中的单稳态电路的数字化和数字锁相环提取位同步信号也进行了详细的设计说明。实际应用结果表明, 系统工作稳
定可靠, 设计是成功的。(Describes the digital voice communications, the use of in-system programmable technical and complex programmable logic device CPLD, to achieve the digital voice multiplexer and demultiplexer for the single steady state in which the digital circuit and digital phase locked loop extraction bit synchronization signals are also carried out a detailed design specification. The practical application results show that the system works stable and reliable design is successful.)
- 2020-12-01 10:39:28下载
- 积分:1
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eDP
eDP接口TFT-LCD显示驱动原码(verilog+c)(eDP Interface TFT-LCD display driver source code (verilog+c))
- 2020-10-17 09:17:27下载
- 积分:1
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JOP kernel source code cache, not easy to find, we must kits
JOP的内核缓存源码,不易找到,大家一定要顶啊-JOP kernel source code cache, not easy to find, we must kits
- 2022-01-27 18:39:54下载
- 积分:1
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BLUE
说明: 利用EGO1数模混合口袋实验平台上的蓝牙模块与板卡进行无线通信。使用支持蓝牙 4.0 的手机与板卡上的蓝牙模块建立连接,并且通过手机 APP 发送命令,控制 FPGA 板卡上的硬件外设。(The Bluetooth module on the EGO1 digital-analog mixed pocket experimental platform is used to communicate with the board. The Bluetooth 4.0-enabled mobile phone is used to establish a connection with the Bluetooth module on the board, and commands are sent through the mobile phone APP to control the hardware peripherals on the FPGA board.)
- 2020-06-24 02:00:02下载
- 积分:1
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这是一个时钟的VHDL源代码,其中包含了源代码,以及工程。
这是一个时钟的VHDL的源程序,里面包含有源程序,还有工程文件对大家很有帮助-This is a clock VHDL source code, which contains the source code, as well as engineering documents helpful to everyone
- 2023-03-26 14:20:04下载
- 积分:1
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以前在学校里的课程设计,使用verilog编写的一个CPU程序,可以下板子...
以前在学校里的课程设计,使用verilog编写的一个CPU程序,可以下板子-Ago in the school curriculum design, the use of Verilog CPU prepare a procedure under the board
- 2022-01-20 22:48:37下载
- 积分:1
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cpu
cache,实现了部分简单指令,仿真模拟确认可行(Single-cycle CPU, to achieve some simple instruction, simulation confirm feasible)
- 2015-01-05 14:11:10下载
- 积分:1
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基于VHDL的UART控制器设计
UART模块的VHDL语言设计(Design of VHDL language based on UART module)
- 2017-11-13 23:56:26下载
- 积分:1
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dac_spi
DA9125 配置spi程序 正弦波产生(DA9125 configuration spi program sine wave generated)
- 2017-05-27 20:17:40下载
- 积分:1