-
freq
vhdl八位十进制数字频率计的设计,顶层和数码管扫描模块(vhdl eight decimal digital frequency meter design, top-level and digital tube scanning module)
- 2012-10-09 15:09:22下载
- 积分:1
-
由VHDL 语言实现的数控分频
利用的是QUARTUES环境已经得到验证...
由VHDL 语言实现的数控分频
利用的是QUARTUES环境已经得到验证-By the NC VHDL language is the use of sub-frequency QUARTUES environment has been tested
- 2023-01-20 00:20:04下载
- 积分:1
-
RS
通过verilog hdl语言实现RS编码器与译码器的设计(Verilog hdl language through the RS encoder and decoder design)
- 2021-04-28 15:48:44下载
- 积分:1
-
S05_example_Network
vivado lwip 应用文档 基于zynq 7020(vivado lwip example text of zynq)
- 2020-06-17 11:40:02下载
- 积分:1
-
ethernet_loopback
通过FPGA驱动千兆以太网口,完成SPARTAN6上的UDP数据包闭环测试,即通过网口发送数据包到FPGA,FPGA内部将接收到的数据返回到PC机,建议测试之前添加ARP静态绑定,FGPA内部的IP以及MAC地址在ROM里的COE文档里可以看到,发送端添加了CRC以及整体CHECKSUM的计算(Driven by FPGA Gigabit Ethernet port, UDP SPARTAN6 data packet on the closed loop test, through the network to send data packets to FPGA, FPGA will receive the data back to the PC, the proposed test before adding ARP static binding, FGPA internal IP and MAC address in the COE document in the ROM where you can see, the sender adds CRC and CHECKSUM integral calculation)
- 2017-11-20 10:21:38下载
- 积分:1
-
Over_Current_Relay_Co_ordination
try this for pq improvmnett
- 2012-11-17 05:40:30下载
- 积分:1
-
FPGA控制AG9226代码
FPGA控制AG9226进行采样的代码,并用signaltap测试了一下其正确性
- 2022-07-21 15:41:56下载
- 积分:1
-
vlog_flash_20090712.tar
说明: NAND FLASH的多个仿真模型,可以用于接口设计的测试(NAND FLASH multiple simulation model that can be used for the test interface design)
- 2009-08-05 21:14:07下载
- 积分:1
-
可实现找钱功能的自动售邮票机,可买两种邮票,一元的和五角的...
可实现找钱功能的自动售邮票机,可买两种邮票,一元的和五角的-Money function can be realized stamp vending machine, to buy two stamps, one dollar and the Pentagon
- 2022-07-09 12:07:56下载
- 积分:1
-
super fast debounce button on vhdl, xilinx xc
super fast debounce button on vhdl, xilinx xc
- 2022-10-30 03:20:04下载
- 积分:1