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Frame-synchronization
FPGA 帧同步源代码 调试无错误 ALTERA 平台(Frame synchronization
FPGA)
- 2011-06-21 10:41:22下载
- 积分：1
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e_BIU
说明： isa MEMORY PLAN eu biu asm
- 2020-06-25 19:20:02下载
- 积分：1
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Verilog语法
说明： Verilog语法教程，适合初学者，详细(Verilog instruction book)
- 2019-05-04 16:07:18下载
- 积分：1
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Hamming_decoder-1
this program does something im not sure what but all i want is to get into the damn site thank you
- 2010-09-09 16:46:51下载
- 积分：1
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SineGen
Basic VHDL code to create a sine wave generator for an FPGA board.
- 2014-01-24 01:04:15下载
- 积分：1
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vjtag
说明： quartus vitual jtag代码使用接口，通过该接口模板方便使用者通过jtag在线读取FPGA的数据。(The quartus virtual JTAG code uses an interface, through which users can read FPGA data online.)
- 2020-05-06 09:42:50下载
- 积分：1
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VGAtuxiangxianshi
用FPGA实现 VGA显示的图像显示控制器设计
用VHDL实现 硬件实现是屏幕上面出现彩色条纹(VGA display with FPGA image display controller design
Using VHDL hardware implementation is colored stripes appear above the screen)
- 2014-05-19 14:07:57下载
- 积分：1
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VHDL--VGA
此VHDL语言程序可以控制液晶屏幕任意动画播放(The VHDL language program can control the LCD screen any animation)
- 2015-03-27 18:44:28下载
- 积分：1
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gtwizard_254_127_ex_1113_3
配置GTH ip的例子工程，选用7 series 芯片的GTH 113quad的四个通道，在程序中每个链路利用自己的恢复时钟进行数据解码，所以四个通道可以各自独立运行；成功工作在2.54Gb/s的链路状态，长时间（>24小时）的测试，误码率一直为0.(The GTH ip example project is configured with four channels of the GTH 113quad of the 7 series chip. Each link in the program uses its own recovery clock for data decoding, so the four channels can operate independently; the successful operation is at 2.54Gb/ The link state of s, long time (>24 hours) test, the bit error rate has been 0.)
- 2019-06-17 21:33:56下载
- 积分：1
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SD_rtl
用verilog实现sd卡读写，亲测可用(Implementation of SD card read and write with Verilog)
- 2020-12-27 21:49:02下载
- 积分：1
