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sp6des
串行数据开发实用代码， 适合初级学习者使用 很不错(Serial data to develop a practical code for primary learners use very good)
- 2013-01-10 14:54:11下载
- 积分：1
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std_ovl_v2p7_Feb2013
目前最新的OVL库，里面是标准的ASSERTION模块，支持VHDL刚Verilog，最近在做AXI协议验证的时候用到，分享下(The latest OVL(open verification library),including all standard module of assertions(VHDL and Verilog). It can be used into AXI Protocl Verification. Just share with you guys.)
- 2021-04-28 21:38:43下载
- 积分：1
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mooor状态机的VHDL程序，代码，状态机，关键是分析各个状态之间的切换...
mooor状态机的VHDL程序，代码，状态机，关键是分析各个状态之间的切换-mooor zhuangtaiji zhuagtaiji guanjianshi gege zhuangtai zhijian de qiehuan
- 2022-02-06 05:30:36下载
- 积分：1
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vhdl_lms
vhdl 语言实现的lms算法的自适应滤波器 两种实现方式 包括改进(VHDL language lms algorithm adaptive filter implemented in two ways including improved)
- 2012-04-26 18:15:02下载
- 积分：1
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uartfifo
串口通信例程，使用FIFO数据缓存。Verilog源码，基于FPGA的uart开发，加深理解。(uart communication)
- 2017-04-20 22:16:21下载
- 积分：1
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8-Multipliers
国外大学上课用PPT。关于乘法器架构，实现，优化，有booth算法的具体实例。(Foreign university classes PPT. About multipliers architecture, implementation, optimization, there is a specific instance of the booth algorithm.)
- 2012-12-06 21:57:36下载
- 积分：1
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traffic 2
说明： 实现主干道交通灯显示，以状态机程序实现，并用数码管进行红绿灯倒计时的显示，内置计数模块，交通灯控制模块，数码管显示模块，并对各模块用电路图的方式进行连接。对于学习VHDL语言有所帮助。(The main road traffic light display is realized by the state machine program, and the digital tube is used to display the traffic light countdown. The counting module, the traffic light control module and the digital tube display module are built in, and each module is connected by the circuit diagram. It is helpful for learning VHDL.)
- 2020-06-25 19:55:12下载
- 积分：1
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cnt24_t
这是二十四进制计数器的源程序，有需要的同学可以参照一下！(This is 24 hexadecimal counter source, needy students can refer to you!)
- 2008-12-22 09:29:29下载
- 积分：1
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SPI的verilog代码的可编程时钟
SPI Verilog code with programmable clock
- 2022-10-30 18:55:03下载
- 积分：1
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altera de2 开发板 vga lcd控制quatus 工程
altera de2 开发板 vga lcd控制quatus 工程-altera de2 board vga lcd control quatus works
- 2023-05-15 10:55:03下载
- 积分：1
