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BPSK
FPGA实现BPSK调制,带Modelsim仿真,实际系统测试通过,载波信号,调制波信号频率可调(FPGA implementation BPSK modulation with Modelsim simulation, the actual system test, the carrier signal, modulated wave signal frequency adjustable)
- 2020-10-30 22:09:56下载
- 积分:1
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The document may download to FPGA chip to complete the clock divider,serial
本文件是可以直接使用下载到FPGA里面使用,里面包含时钟分频电路,串并转换和并串转换电路,多通道信号加权的乘加电路等。-The document may download to FPGA chip to complete the clock divider,serial-to-parallel,parallel-to-serial,and multiple-add circuit for multiple channels weight calculation
- 2022-09-03 00:05:03下载
- 积分:1
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sos_module
用FPGA实现sos摩尔密码,即输出电平信号短长短。就是有次序的控制输出莫斯密码的“点”,“画”和“间隔”。而 control_module.v 是一个简单的定时触发器,每一段时间都会使能sos_module.v。(Realized by FPGA sos mole password, the output signal level of short duration. There is a sequence of output control points Moss password, painting and intervals. And control_module.v is a simple timer triggers, each period of time will enable sos_module.v.)
- 2016-09-20 16:26:29下载
- 积分:1
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QPSK_System
实现QPSK系统的调制解调仿真,基带成形滤波器采用升余弦滚降滤波器,将仿真的误码率与理论误码率作了比较(Implement QPSK modulation and demodulation simulation system, the baseband shaping filter using Raised Cosine filter will BER simulation were compared with the theoretical BER)
- 2020-12-22 15:39:07下载
- 积分:1
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附件 介绍了如何 使用compxlib命令编译Xilinx的ModelSim仿真库,创建这个仿真库对ISE调用modelsim是必不可少的一步,该法完全自动化,...
附件 介绍了如何 使用compxlib命令编译Xilinx的ModelSim仿真库,创建这个仿真库对ISE调用modelsim是必不可少的一步,该法完全自动化,免去繁杂的手动操作,是创建这个仿真库最简洁的方法之一-Annex compxlib introduce how to use Xilinx
- 2022-03-15 17:10:01下载
- 积分:1
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Digital-System
A complete VHDL source code to 5-storey elevator
- 2014-09-05 11:24:26下载
- 积分:1
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Verilog HDL for Half Adder, Full Subtractor, Half Subtractor and 2x4 decoder.
Verilog HDL for Half Adder, Full Subtractor, Half Subtractor and 2x4 decoder.
- 2022-07-06 17:29:44下载
- 积分:1
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doing more of a state machine on the three described earlier. Many more informat...
自己做的一个关于more状态机的三种描述的比较。以后会有更多的资料,请大家关注。-doing more of a state machine on the three described earlier. Many more information, please everyone"s attention.
- 2022-02-12 02:20:30下载
- 积分:1
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去抖动状态机,外部按键转换状态,同时可去抖动
去抖动状态机,外部按键转换状态,同时可去抖动-To shake state machine, the external key conversion state, while to the jitter
- 2022-02-07 09:04:28下载
- 积分:1
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world clock
世界时钟,最简单的vhdl的fpga设计,是vhdl语言的入门级,jigon供参考娱乐
- 2022-01-28 20:54:25下载
- 积分:1