-
VendingMachine
VHDL Vendingmachine source
- 2013-11-02 06:19:46下载
- 积分：1
-
ripple adder
设计的结构是纹波进位加法器架构，但执行的操作是32位加法和32位减法
- 2023-07-02 19:50:04下载
- 积分：1
-
gtx_aurora_zc706_example
Aurora 8B/10B协议是Xilinx公司针对高速传输开发的一种可裁剪的轻量级链路层协议，通过一条或多条串行链路实现两设备间的数据传输。协议Aurora协议可以支持流和帧两种数据传输模式，以及全双工、单工等数据通信方式。(The Aurora 8B / 10B protocol is a tailor-made lightweight link layer protocol developed by Xilinx for high-speed transmission that enables data transfer between two devices over one or more serial links. Protocol Aurora protocol can support two data transfer modes, stream and frame, as well as full-duplex, simplex and other data communications.)
- 2018-01-23 08:53:37下载
- 积分：1
-
v5_emac
以太网的FPGA程序实现以太网的FPGA程序实现以太网的FPGA程序实现(enternet verilog fpga)
- 2013-12-15 23:08:11下载
- 积分：1
-
VGA FPGA时序仿真，仿真的PS / 2键盘接口VHDL源C.
用FPGA模拟VGA时序、模拟PS/2总线的键盘接口VHDL源代码，基于Xilinx spartan3-VGA FPGA timing simulation, simulation PS/2 keyboard interface bus VHDL source code, Based on Xilinx spartan3
- 2023-01-19 01:15:04下载
- 积分：1
-
verilog___UART
Verilog 编写的串口通信模块 带测试代码(Verilog prepared by the serial communication module with a test code)
- 2012-05-24 20:38:27下载
- 积分：1
-
VHDL_to_UART
用VHDL编写的串口通讯程序，包括几个不同的程序例子，也可以用verilog进行改写。()
- 2007-08-09 09:54:40下载
- 积分：1
-
mdio
使用verilog语言进行编码 完成mdio接口访问phy8201芯片的功能(Use verilog language to encode the mdio interface to access the function of phy8201 chip)
- 2018-09-18 14:20:40下载
- 积分：1
-
这是一个也介绍GPIB编程的文章以及介绍GPIB协议规范
这是一个也介绍GPIB编程的文章以及介绍GPIB协议规范-This is a GPIB programming also introduced the article and introduce GPIB norm
- 2022-06-29 19:43:11下载
- 积分：1
-
sobel
由Verilog编写在FPGA实现sobel算法应用于图像边缘检测，工程文件可在quartus13.1以上版本打开；工程使用到ram、fifo、pll三种ip核，design文件夹下包含ram、fifo、vga控制以及串口收发和sobel算法模块，sim和doc文件夹下分别包含modelsim的仿真模块和仿真结果；测试时将200*200分辨率的图片用matlab文件夹下的matlab脚本压缩、二值化，再将生成文件中数据用串口发给FPGA，边缘检测结果会通过VGA输出。(Written by Verilog in the FPGA implementation sobel algorithm applied to the edge detection of the image, the project file can be opened in the quartus13.1 or later project use ram, fifo, pll three ip kernel, design folder contains ram, fifo, vga control and Serial port transceiver and sobel algorithm module, sim and doc folder, respectively, include modelsim simulation module and simulation results test will be 200* 200 resolution picture matlab folder under the matlab script compression, binarization, and then generated Data in the file with the serial port to the FPGA, edge detection results will be output through the VGA.)
- 2021-01-15 21:08:46下载
- 积分：1
