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adding
加法器，输入两个整数，用电路图形式将其逻辑原理呈现出来，该加法器为8位运算，每一位都对应一张电路图，可展示其完整过程(Adder, input two integer, with circuit diagram form its logical principle appear, this adder is 8 bit arithmetic, each corresponding to a circuit diagram, can show the complete process)
- 2012-11-19 13:54:32下载
- 积分：1
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EEPROM_at25320a
Commponent for drivering EEPROM memory AT25320 from Avalon bus.
- 2013-11-22 00:04:04下载
- 积分：1
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vga
VGA驱动及显示程序，用Verilog编写代码实现VGA的驱动和显示，并且提供了测试程序Testbench通过测试能得到正确的时序波形。(the source code for driving VGA and displaying the images,the testbench was offered.)
- 2009-06-11 19:05:09下载
- 积分：1
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一些较为经典的VHDL代码,专注于信号分析与检测方面
一些较为经典的VHDL代码,专注于信号分析与检测方面-Some of the more classic of the VHDL code, focusing on signal analysis and testing
- 2022-02-04 20:13:26下载
- 积分：1
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VHDL，verilog串并转换源程序
Xilinx公司参考资料
VHDL，verilog串并转换源程序
Xilinx公司参考资料-VHDL, verilog Series and conversion company Xilinx reference source
- 2023-04-26 17:40:03下载
- 积分：1
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LIP6903CORE_CSC_RGB2YUV
CSC RGB2YUV Verilog source code
- 2011-02-28 20:06:13下载
- 积分：1
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LMS
用verilog编写的lms算法。可实现自适应滤波功能(Lms algorithm written in verilog. Adaptive filtering can be achieved)
- 2021-05-15 11:30:02下载
- 积分：1
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在spartan－3e上利用八个led实现流水灯效果
在spartan－3e上利用八个led实现流水灯效果-Spartan-3e in the use of eight led lights to achieve the effect of flowing water
- 2022-03-21 18:10:29下载
- 积分：1
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VHDL
用VHDL语言实现一Mealy型时序电路，并做时序仿真和功能仿真检验正确与否。(Implement a Mealy-type sequential circuits using VHDL language, and do functional simulation and timing simulation test correct.)
- 2014-03-20 14:44:28下载
- 积分：1
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用VHDL写的运动计时表程序，用Modelsim仿真已经通过，帖出来与大家分享。...
用VHDL写的运动计时表程序，用Modelsim仿真已经通过，帖出来与大家分享。-write VHDL campaign time table program, Modelsim simulation has been passed, Tie up share with you.
- 2022-01-26 05:57:13下载
- 积分：1
