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FIFO2
用verilog HDL语言编写的fifo存储器源文件 (Using Verilog language HDL FIFO memory source file)
- 2012-03-08 09:12:18下载
- 积分：1
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TugasUAS_AuditTI_1504505017_Reguler
ertyguhijop[lkjhvbn hiouopi][[poiuy
- 2019-02-05 09:18:23下载
- 积分：1
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OFDM_CP
ofdm系统的matlab实现，包括插入导频信号和循环前缀(Matlab implementation of ofdm system, including inserted pilot frequency signal and the cyclic prefix)
- 2013-05-29 10:10:23下载
- 积分：1
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verilog例子很丰富，几个经典的,希望对初学者有所帮助
verilog例子很丰富，几个经典的,希望对初学者有所帮助-verilog examples of very rich, a few classic, and want to be helpful for beginners
- 2023-03-17 19:05:03下载
- 积分：1
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multiply
由verilog编写的乘法器，通过两个文件的调用实现。由于子模块的调用使得程序简化了许多。(Prepared by the Verilog multiplier, through the realization of the two documents call. As the sub-modules to simplify the procedure call makes a lot.)
- 2008-12-30 20:51:33下载
- 积分：1
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0 2
说明： 基于labVIEW，控制电机等工作实例，程序基本完整(Based on labVIEW, control motor and other working cases, the program is basically complete)
- 2018-01-24 09:09:20下载
- 积分：1
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MT9M001
FPGA驱动MT9M001的verilog代码，里面还有ddr3部分将图像数据进行存储，lcd进行图像显示，里面的摄像头驱动部分很详细，大家可以多研习研习(Verilog driver MT9M001 code, which is also the DDR3 image data storage, LCD display, which drives the part is very detailed, we can learn more)
- 2020-07-10 13:48:54下载
- 积分：1
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VHDL language design stopwatch, timer function of the realization, the realizati...
VHDL语言设计的秒表，实现计时功能，实现报时功能，并且通过硬件实验。-VHDL language design stopwatch, timer function of the realization, the realization of time functions, and through hardware experiments.
- 2022-09-16 02:55:02下载
- 积分：1
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USB_devide
利用最新的嵌入式开发工具EDK，在FPGA 中完成对PDIUSBD12 的硬件定制和固件编程，从而在FPGA
中实现U S B 控制器， 并最终完成U S B 的枚举过程、驱动程序的开发和简单的应用。(Using the latest embedded development tools, EDK, in the FPGA completes its PDIUSBD12 custom hardware and firmware programming, in order to realize USB controller in the FPGA, and ultimately complete the USB enumeration process of driver development and simple应用.)
- 2007-10-04 16:27:44下载
- 积分：1
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Xcell1
W elcome to X CELL, the new
Xilinx customer newsletter.
By sending us your development
system registration card you automatically
became n charter subscriber
to this quarterly publication. It is our
intent to make this an informative,
easy to read, responsive and-hopefully-
interactive newsletter. We
want to supply you with early and
correct information, tell you about
the status of our products and about
our plans, about bugs and their workarounds,
give you applications ideas
and convey to you some of the en thusiasm
that we feel for our Programmable
Gate Arrays.
If you have questions or suggestions,
please send them to me. II Letters
to the Editor make a newsletter
more lively.
Peter Alfke, Editor
- 2014-12-25 01:07:59下载
- 积分：1
