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可编程逻辑设计快速入门指南从西林有限
Programmable Logic Design Quick Start Guide from Xilin Co.
- 2022-03-19 03:08:54下载
- 积分:1
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crc_verilog_xilinx
各类CRC效验码 有CRC8-8 CRC16-8 CRC32-8 CRC12-4 CRC-CCIT-8(CONTAIN CRC8-8 CRC16-8 CRC32-8 CRC12-4 CRC-CCIT-8 )
- 2021-03-10 22:59:26下载
- 积分:1
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fpga--lpass
基于FPGA的数字低通滤波器 。。。。。(FPGA-based digital low-pass filter。。。。。)
- 2021-04-24 08:28:47下载
- 积分:1
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MTD_MTI
(1)MTI
(2)用FFT实现MTD
(3)用FIR滤波器实现MTD
((1) MTI (2) using FFT realization MTD (3) with the FIR filter implementation MTD)
- 2020-11-04 16:39:52下载
- 积分:1
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that I wrote four string and turn ISE code In xilinx Spartan3E debugging has bee...
这是我自己写的4位并转串ISE代码,在xilinx Spartan3E 上已经调试成功,拿出来与大家分享!-that I wrote four string and turn ISE code In xilinx Spartan3E debugging has been successful, with the show to share with you!
- 2022-02-14 20:17:51下载
- 积分:1
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VGA控制器的VHDL,得出3条线
vga controller vhdl, it draws 3 lines -vga controller vhdl, it draws 3 lines
- 2022-01-25 16:45:25下载
- 积分:1
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LCD_test
this a example for the LCD for altera FPGA cyclone ii EP2C8. implemented in verilog. tested using altera EP2C8 fpga
- 2013-07-25 14:43:43下载
- 积分:1
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polar_encoder_1024 (1)
该部分的主要功能是完成基于FPGA的polar码编码。(The main function of this part is to complete the FPGA-based polar code coding.)
- 2021-01-10 16:58:50下载
- 积分:1
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Fractional_Time_Delay
Used for Time shifting discrete signals, it can do both integral and fractional sampling period delay. Original.
- 2020-12-16 22:29:12下载
- 积分:1
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Tuart_tx_rxh
该工程用verilog编写,已通过串口调试助手调试通过,接收模块采采用8倍波特率采样数据,有较好的滤波功能,在PC上完成自发自收功能。
(The project is written in verilog debugging through serial debugging assistant, adopted 8 times the baud rate sampling data receiver module, better filtering done on the PC spontaneous self-closing function.)
- 2012-08-26 10:39:49下载
- 积分:1