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DDSN
quartus II 13.0 DDS工程文件,采用VHDL编写,可输出正交两路正弦信号。可以直接用modelsim-alter 仿真(quartus II 13.0 DDS project file, using VHDL written two orthogonal sinusoidal output signals. Can be simulated directly modelsim-alter)
- 2021-03-20 16:49:17下载
- 积分:1
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vivado 从此开始配套资料
vivado入门使用介绍,初学者入门学习(vivado Instructional pdf)
- 2020-07-04 18:00:01下载
- 积分:1
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8位大小比较器
说明: 8位大小比较器的VHDL源代码,Magnitude Comparator
VHDL description of a 4-bit magnitude comparator with expansion inputs(eight compared with the size of the VHDL source code, Magnitude Comparator VHDL description of a 4-bit magnitude comparator inputs with expansion)
- 2005-10-28 22:35:12下载
- 积分:1
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Analog-Digital-Wandler
关于逻辑信号的转变等等的一个程序。还包括显示(Analog-Digital-Wandler)
- 2009-11-07 20:20:28下载
- 积分:1
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AHBtoAPB
AHBtoAPB设计基于AMBA总线协议的APB Bridge设计(AHB to APB designThe AHB to APB bridge interface is an AHB slave. When accessed (in normal operation or system test) it initiates an access to the APB.)
- 2012-01-30 12:47:15下载
- 积分:1
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prepared using VHDL stepper motor control methods. For your reference.
用VHDL编写的步进电机控制方法.供大家参考用.-prepared using VHDL stepper motor control methods. For your reference.
- 2022-06-16 01:54:04下载
- 积分:1
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turbo_encoder
在赛灵思的FPGA上实现turbo码的编码程序,使用Verilog语言实现。(Implemented on Xilinx FPGA in the turbo coding principle, the use of Verilog language.)
- 2021-04-19 09:38:51下载
- 积分:1
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M4A564/32 CPLD VHDLA程序,调试可用,51扩展.
M4A564/32 CPLD VHDLA程序,调试可用,51扩展.-M4A564/32 CPLD VHDLA procedures, debugging is available, 51 to expand.
- 2023-08-25 16:25:03下载
- 积分:1
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FSK
频移键控FSK的Verilog实现,带测试文件,并在FPGA开发板上成功验证(Frequency Shift Keying FSK the Verilog implementation, with the test file, and successfully verified in FPGA development board)
- 2020-09-03 11:28:07下载
- 积分:1
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rams
combinatorial modules
- 2019-04-13 19:41:21下载
- 积分:1