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UART_prj_ViHDL
vhdl project at sbu uni in iran
uart
- 2010-05-08 16:18:37下载
- 积分:1
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cmsdk_apb_timer
说明: 关于计时器 verilog语言,采用arm架构的m3,可以直接应用于soc(About timer verilog language, USES the arm architecture of m3, can be directly applied to soc)
- 2021-04-26 12:38:45下载
- 积分:1
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This tutorial explains how the SDRAM chip on ltera’s DE2 Development and Educati...
This tutorial explains how the SDRAM chip on ltera’s DE2 Development and Education board can be used with a Nios II system implemented by using the Altera SOPC Builder.
- 2022-02-12 08:59:26下载
- 积分:1
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exp12
说明: 浙江大学计算机组成实验12指令扩展多周期CPU实现(The implementation of 12 instruction extended multi cycle CPU in Computer Composition Experiment of Zhejiang University)
- 2020-10-09 16:17:35下载
- 积分:1
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LPC总线从设备的verilog设计,包含状态机和中断功能。
LPC总线从设备的verilog设计,包含状态机和中断功能。-verilog code for LPC device
- 2022-01-28 17:10:12下载
- 积分:1
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FFT_verilog
说明: verilog实现的FFT变换,经硬件测试其功能与Altera的FFT IP核相近(verilog implementation FFT transform, through hardware, test its functionality with Altera' s FFT IP core similar to)
- 2009-08-26 11:29:57下载
- 积分:1
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chaotic_1d
说明: 一维超混沌随机数的生成verilg,还有testbench仿真激励,modelsim的仿真工程。(The generation of one-dimensional hyperchaotic random number verilg, testbench simulation stimulation and Modelsim simulation engineering.)
- 2020-05-11 12:45:42下载
- 积分:1
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74ls138-integral-4-wire-encoder-16
74ls138组成16..4线编码器 经过本人验证(74ls138 composed of 16 .. 4 line encoder after I verify)
- 2011-09-20 19:00:59下载
- 积分:1
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vhdl,七段数码管驱动程序,完成数字显示功能
vhdl,七段数码管驱动程序,完成数字显示功能-vhdl, seven-segment digital tube driver, complete the digital display
- 2022-03-19 02:05:40下载
- 积分:1
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QPSK
说明: 基于FPGA的QPSK调制解调电路设计与实现 (QPSK)
- 2010-04-07 14:15:21下载
- 积分:1