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05_key_test
fpga key test 入门 xilinx 黑金的板子(fpga key test xilinx)
- 2017-07-27 09:27:58下载
- 积分:1
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非常优秀的国外VHDL设计教程,可进行MODELSIM模拟等操作
非常优秀的国外VHDL设计教程,可进行MODELSIM模拟等操作-Excellent foreign VHDL design tutorial, it can conduct operations such as ModelSim Simulation
- 2023-05-15 08:55:03下载
- 积分:1
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AD7980
AD9850 VERILOG代码 硬件验证过,可以使用。
- 2021-05-07 15:37:36下载
- 积分:1
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clock_6
说明: ds1302时钟驱动程序,已在quartus上验证可以是直接使用(DS1302 clock driver, which has been verified on quartus, can be used directly)
- 2020-06-24 12:00:02下载
- 积分:1
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pedometer
本文设计了基于加速度传感器的计步器,并通过仿真以及实际调试得到了相应的结果的记录。本实验首先通过加速度传感器检测目标物体的运动,产生脉冲,将脉冲放大后经过施密特触发器整型为方波,并给出了方波的调试电路图。然后编写程序,利用D触发器检测方波的上升沿,当上升沿到来时,计数,并对十位、个位分别编码,然后由使能信号交替控制数码管输出结果。本文给出了仿真以及调试的程序、结果。(This article is designed pedometer-based acceleration sensor and the corresponding results recorded by simulation and debugging. The experiments by first acceleration sensor detects the movement of the target object, generates a pulse, the pulse amplification is a square wave after the Schmitt trigger integer, and gives the the debug circuit diagram of a square wave. Then write procedures, the use of the rising edge of the detection of the square wave of the D flip-flop, when the rising edge, the count, and ten bits are encoded, and then alternately by the enable signal output of the digital control. In this paper, a simulation and debugging procedures, results.)
- 2013-03-13 08:58:22下载
- 积分:1
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FPGA-Racing-Game
在开发板EGO1上实现赛车游戏,语言为verilog,内含bits文件(racing game in verilog)
- 2020-12-24 13:39:07下载
- 积分:1
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高速高性能FFT处理器的VLSI实现研究,适合做FPGA的技术人员参考研究FFT...
高速高性能FFT处理器的VLSI实现研究,适合做FPGA的技术人员参考研究FFT-High-speed high-performance FFT processor VLSI realization of research, suitable for FPGA technology reference study FFT
- 2022-05-30 23:35:49下载
- 积分:1
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[verilog]dcfifo_256x32
双时钟域FIFO(This is self-defined Dual-Clock FIFO, using logic lut resources.
Dual-Clock FIFO,
Depth: 256
Width: 32
USEDW: Y
FULLL:Y
EMPTY:Y)
- 2017-05-10 13:25:41下载
- 积分:1
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HDB3
用Verilog HDL语言进行HDB3编码,并通过Quartus Ⅱ仿真验证(With the Verilog HDL language HDB3 coding, and simulation by Quartus Ⅱ)
- 2020-11-30 11:19:28下载
- 积分:1
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VHDL-Code-For-Full-Adder-By-Data-Flow-Modelling
VHDL Code For Full Adder By Data Flow Modelling
- 2013-11-08 00:39:04下载
- 积分:1