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FFT
很好的fft学习程序感兴趣的同学可以看哈,下载一下。(it is very good )
- 2012-04-04 16:00:42下载
- 积分:1
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latticeECP3-serdes-test-code
lattice ECP3系列高速FPGA serdes测试代码(lattice ECP3 series high speed serdes test code)
- 2021-03-25 01:39:14下载
- 积分:1
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within waveform generator, Adder, classic dual
内有波形发生器,加法器,经典双进程状态机,伪随机熟产生器,相应加法器的测试向量,16×8bit RAM,FIFO,通用RAM等源程序-within waveform generator, Adder, classic dual-process state machine, cooked pseudo-random generator, the corresponding Adder test vector, 16 x 8bit RAM, FIFO, etc. source generic RAM
- 2023-09-02 09:40:03下载
- 积分:1
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电梯的游戏
在 VHDL 中实现的游戏
实施LFSR创建与随机游戏板
随机颜色。使用VGA控制器和块内存
我们显示游戏板,并写入它取决于某些规则。用户
可以控制如何密游戏板填充,则显示什么颜色,
而如何快速模拟。
- 2022-03-01 01:26:24下载
- 积分:1
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shukongfenpinqi
数控分频器的设计
数控分频器的功能就是当在输入端给定不同输入数据时,将对输入的时钟信号有不同的分频比,例3的数控分频器就是用计数值可并行预置的加法计数器设计完成的,方法是将计数溢出位与预置数加载输入信号相接即可。(NC NC divider divider design of its function is when the input given different input data, input the clock signal will have different frequency than, for example 3 is to use the NC prescaler count preset value of the adder parallel counter design is completed, the method is to count the number of overflow bit with preset load to the input signal phase.)
- 2008-12-13 09:56:51下载
- 积分:1
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QPSK
用Verilog语言实现QPSK调制,QPSK是一种数字调制方式。它分为绝对相移和相对相移两种。
(Verilog language using QPSK modulation, QPSK is a digital modulation. It is divided into absolute and relative phase shift of the phase shift of two.)
- 2011-01-24 17:46:44下载
- 积分:1
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VHDL_COUNTING 与 4 使脉冲和使用 3 按钮了,下来,停止 (Mạch đếm với 4 xung ENA sử dụng 3 nút nhấn lên,xuống và dừng l
VHDL_COUNTING 与 4 使脉冲和使用 3 按钮了,下来,停止 (Mạch đếm với 4 xung ENA sử dụng 3 nút nhấn lên,xuống và dừng lại)
- 2022-03-19 05:46:27下载
- 积分:1
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asynchronous-fifo
同步fifo的调用程序,调用Quartus II 9.0 (32-Bit)中的fifo模块(Synchronous fifo calling program, call Quartus II 9.0 (32-Bit) in fifo module)
- 2013-08-23 21:58:56下载
- 积分:1
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利用verilog语言设计公共电话共包括以下几个状态:挂机、待机、身份确认、修改密码、通话等五个状态。内含详细的源码以及设计过程、模块...
利用verilog语言设计公共电话共包括以下几个状态:挂机、待机、身份确认、修改密码、通话等五个状态。内含详细的源码以及设计过程、模块-The use of public telephones were verilog language design include the following states: hang up, standby, identification, change passwords, call the five states. Includes a detailed source code as well as the design process, the module
- 2022-02-25 00:52:03下载
- 积分:1
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vga_driver
verilog语言设计的VGA驱动。在Quarus11.0下编译成功,并在Altera cyclone4开发板上测试OK(verilog language design VGA driver. In Quartus11.0 successfully compiled and Altera cyclone4 development board test OK)
- 2016-05-25 17:19:18下载
- 积分:1