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rs_encoder
适应多个模式的rs编码,Verilog,选择对应的多项式(RS coding adapted to multiple modes.)
- 2020-06-16 04:40:02下载
- 积分:1
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VerilogHDL.自动增益控制模块中产生控制电压的部分
VerilogHDL.自动增益控制模块中产生控制电压的部分-VerilogHDL. Automatic Gain Control Module have some control voltage
- 2022-06-19 20:17:38下载
- 积分:1
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本文描述了fpga中的亚稳态时如何产生的,以及如何计算亚稳态的平均无故障时间。对了解亚稳态有帮助。...
本文描述了fpga中的亚稳态时如何产生的,以及如何计算亚稳态的平均无故障时间。对了解亚稳态有帮助。-This paper describes the sub-fpga how the steady state, as well as how to calculate the metastable MTBF. The understanding of metastable helpful.
- 2022-06-01 03:41:23下载
- 积分:1
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lbs_fpga_upld
利用FPGA实现与powerpc的localbus数据接口代码。用verilog实现(localbus interface with PowerPC using Verilog)
- 2020-11-25 22:59:38下载
- 积分:1
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双向移位寄存器的VHDL源程序,自己做实验编写的可以用 谢谢大家...
双向移位寄存器的VHDL源程序,自己做实验编写的可以用 谢谢大家-Bi-directional shift register of the VHDL source code, prepared by their own experiments can be used Thank you
- 2022-02-11 10:52:42下载
- 积分:1
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用Matlab编写fft
在MATLAB下自编实现快速傅里叶分析,(Fast fft own procedures, faster than the system call fft slowe)
- 2020-06-23 09:00:02下载
- 积分:1
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lvds_ctr_top
说明: 用verilog编写的LVDS接口驱动程序,采用IOSERDES技术实现,经过Spartan6 FPGA调试验证,有完整的工程。(The LVDS interface driver written in verilog is implemented using IOSERDES technology. After Spartan6 FPGA debugging and verification, there is a complete project.)
- 2020-03-16 10:29:10下载
- 积分:1
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verilog实现的1024位的大数模逆算法,引入RAM作为数据通道
verilog实现的1024位的大数模逆算法,引入RAM作为数据通道-verilog to achieve the 1024 Modular inverse algorithms, the introduction of RAM as a data channel
- 2022-12-18 20:35:03下载
- 积分:1
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UART
实现了UART的底层协议,加入了控制器,其波特率可以根据使用进行调整;发送模块、接收模块相互独立,互不影响。(Realization of the underlying protocol UART, joined the controller baud rate can be adjusted according to use transmission module, receiver module are independent of each other.)
- 2013-11-30 13:25:21下载
- 积分:1
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verilog full case and paralel case directive usage
verilog full case and paralel case directive usage
- 2022-05-28 07:00:24下载
- 积分:1