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prob1
UART program for fun(UART)
- 2009-11-18 10:26:04下载
- 积分：1
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数字相位
PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the lock data the rising and falling edge; top-level document is PLL.GDF
- 2023-05-28 08:00:03下载
- 积分：1
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breath
说明： 利用verilog写的PWM 程序，来实现产生呼吸灯的效果。(Using xerilog to generate breathing lamp)
- 2020-06-17 04:40:01下载
- 积分：1
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Vending machines, coin
自动售货机，投币自动售货
MaxplusII下运行-Vending machines, coin-operated automatic vending MaxplusII run
- 2022-07-07 06:56:04下载
- 积分：1
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FPGAPDSCDMA
上海交大关于基于FPGA的DSCDMA的实现的毕业设计(Shanghai Jiaotong University based the FPGA DSCDMA, achieve graduation design)
- 2013-02-10 14:31:46下载
- 积分：1
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FM radio decoder and controller VHDL, Xilinx provide. I thank other.
FM收音机的解码及控制器VHDL语言实现，Xilinx提供的．别谢我．-FM radio decoder and controller VHDL, Xilinx provide. I thank other.
- 2022-10-05 04:50:03下载
- 积分：1
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In the Altera chip 2C35F672 platform FFT procedures DSPBuilder5.0, generated Ver...
在Altera芯片2C35F672平台上的FFT程序，采用DSPBuilder5.0，生成Verilog文件。开发环境：QuartusII5.0。-In the Altera chip 2C35F672 platform FFT procedures DSPBuilder5.0, generated Verilog file. Development Environment: QuartusII5.0.
- 2022-03-16 05:08:13下载
- 积分：1
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BCH_EncDec_Matlab
bch编解码的完整版，本人已经做过fpga实现，就是按照该程序为原型，绝对可运行(bch decoding the full version, I have done fpga implementation is in accordance with the procedure for the prototype, can certainly run)
- 2011-10-27 21:55:11下载
- 积分：1
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FIFO2
用verilog HDL语言编写的fifo存储器源文件 (Using Verilog language HDL FIFO memory source file)
- 2012-03-08 09:12:18下载
- 积分：1
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FPGA中实现的硬件UDP 协议
FPGA中实现的硬件UDP 协议 FPGA中实现的硬件UDP 协议
- 2022-03-23 19:25:50下载
- 积分：1
