-
EDA VHDL modules commonly used procedure, the time
EDA中常用模块VHDL程序,不同时基的计数器由同一个外部是中输入时必备的分频函数。分频器FENPIN1/2/3(50分频=1HZ,25分频=2HZ,10分频=5HZ。稍微改变程序即可实现)-EDA VHDL modules commonly used procedure, the time- with a counter by the external input is required when the sub-frequency functions. Frequency Divider FENPIN1/2/3 (50 1HZ frequency = 25 = 2HZ-frequency, frequency = 10 points Stripper. A slight change in procedure can be realized)
- 2022-07-02 21:52:46下载
- 积分:1
-
FPGA
基于FPGA实现的一种新型数字锁相环-FPGA-based realization of a new type of digital phase-locked loop
- 2023-01-20 11:30:04下载
- 积分:1
-
AHBtoAPB
AHBtoAPB设计基于AMBA总线协议的APB Bridge设计(AHB to APB designThe AHB to APB bridge interface is an AHB slave. When accessed (in normal operation or system test) it initiates an access to the APB.)
- 2012-01-30 12:47:15下载
- 积分:1
-
tlm
tlm基本框架,生产消费模型例子
tlm基本框架,生产消费模型例子
tlm基本框架,生产消费模型例子(tlm basic framework, examples of production and consumption model)
- 2010-01-27 17:31:47下载
- 积分:1
-
256字节深度的RS232串口程序,共分4个模块,顶层文件FIFO程序串口收和串口发.经过测试已用于产品.可靠!...
256字节深度的RS232串口程序,共分4个模块,顶层文件FIFO程序串口收和串口发.经过测试已用于产品.可靠!-Depth of 256-byte Serial RS232 procedures, divided into four modules, top-level document procedures FIFO serial and serial-fat collection. After the test has been used in products. Reliable!
- 2022-01-26 06:37:51下载
- 积分:1
-
ProtelDesignInVHDL
说明: Protel中VHDL设计参考,pdf,不错的一本学习VHDL的书(Protel design in VHDL)
- 2009-08-21 11:16:24下载
- 积分:1
-
altera de2 开发板 vga lcd控制quatus 工程
altera de2 开发板 vga lcd控制quatus 工程-altera de2 board vga lcd control quatus works
- 2023-05-15 10:55:03下载
- 积分:1
-
1
matlab code for JTAG cable checking
- 2014-02-04 19:27:39下载
- 积分:1
-
Quartus II
quartus II-sopc builder avalon总线LCD控制IPCORE-quartus II-sopc builder avalon Bus LCD controller IP CORE
- 2022-08-09 10:55:42下载
- 积分:1
-
It is then register ( shifter) PISO ( Parallel
It is then register ( shifter) PISO ( Parallel - in, serial - out)-It is then register ( shifter) PISO ( Parallel- in, serial- out)
- 2022-03-14 08:29:42下载
- 积分:1