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uart_tx
FPGA UART 发送端程序 verilog语言编写
9600波特率 实用(UART transmit side program verilog language 9600 baud)
- 2013-08-14 16:33:34下载
- 积分:1
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用VHDL语言编写的代码,以供大家学习和交流,方便大家学习!...
用VHDL语言编写的代码,以供大家学习和交流,方便大家学习!-prepared using VHDL code for all to study and exchange to facilitate learning!
- 2022-02-04 03:08:53下载
- 积分:1
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uart
UART串口的verilog源代码,完全正确...........(UART serial Verilog source code, completely correct ...........)
- 2009-03-02 14:44:16下载
- 积分:1
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程序采用VHDL:频率合成DDS主要调用LPM,
程序用VHDL实现:
频率合成,DDS
主要调用LPM-procedures using VHDL : frequency synthesis, DDS major call LPM
- 2023-07-07 03:20:03下载
- 积分:1
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test2
说明: 试用Verilog HDL语言,设计十进制计数器,将计数过程用一个数码管进行显示(0~9)。要求首先使用Modelsim软件进行功能仿真,然后使用Quartus软件综合,并下载到开发板进行电路功能测试。(Using Verilog HDL language, a decimal counter is designed. The counting process is displayed by a digital tube (0 ~ 9). It is required to first use Modelsim software for functional simulation, then use quartus software for synthesis, and download to the development board for circuit functional test.)
- 2020-05-17 11:07:28下载
- 积分:1
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eDP
eDP接口TFT-LCD显示驱动原码(verilog+c)(eDP Interface TFT-LCD display driver source code (verilog+c))
- 2020-10-17 09:17:27下载
- 积分:1
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FPGA
学习FPGA的资料,基于FPGA的卡尔曼滤波器的设计与实现(Learning FPGA information, FPGA-based Design and Implementation of Kalman Filter)
- 2010-03-15 21:19:56下载
- 积分:1
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paper_about_polypahse
一篇关于多相滤波器的论文,讲解了关于多信道的实现与仿真。(A paper about the polyphase filter,explained about the realization of multi-channel and simulation
)
- 2014-11-21 22:32:22下载
- 积分:1
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ddr_sdr_V1_1
its the vhdl stuff for ddr sdram controller nice one easily understandable
- 2010-09-08 08:32:09下载
- 积分:1
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用VHDL编写的RS232串口的通信程序
用VHDL编写的RS232串口的通信程序-Written with the VHDL serial RS232 communication program
- 2022-05-06 01:41:31下载
- 积分:1