-
2MW_wind_grid_inverter
针对兆瓦级风电并网逆变器主电路研制中存在的并联扩容、开关频率较低和LCL滤波器难以优化设计等问题，提出了采用交流侧串接电感再进行并联的均流方案，采用载波移相技术提高变流器的等效开关频率，提出了LCL滤波器的设计原则，并给出了上述设计的理论依据和实现方法。通过对2兆瓦风电变流器主电路的仿真验证了上述技术方案。(MW-class wind power for grid-inverter main circuit of the parallel development of existing capacity, a lower switching frequency and LCL filter design difficult to optimize the problem, a series inductor AC side in parallel are further flow program, the use of carrier phase-shifting technology to enhance the equivalent converter switching frequency, a LCL filter design principles, and gives the above-mentioned theoretical basis for the design and implementation. 2 MW of wind power converter main circuit simulation program to verify the above-mentioned technology.)
- 2009-04-28 09:16:38下载
- 积分：1
-
can总线
说明： SJA1000的ip核和相关测试脚本,OPENCORES 下载(SJA1000 IP downloads from opencores)
- 2019-11-15 10:07:14下载
- 积分：1
-
FPGA_SSI
说明： 文档中的verilog代码实现了FPGA与SSI总线的数据协议链接(Verilog code in the document of the FPGA data bus protocol and SSI links)
- 2021-04-19 17:08:51下载
- 积分：1
-
这是我的毕业设计的SVPWM使永磁交流同步电动机…
这是我毕业设计做的一个SVPWM同步永磁交流电机的控制系统，里面除了一个SVPWM的驱动算法之外，还有一个步进电机的控制器，以及基于QUARTUS7.2的NIOS II控制核心，通过PC的串口可以控制同步永磁交流电机和步进电机进行精确的定位。该系统较复杂，运用的知识也比较多，在SVPWM算法，PID算法，步进电机控制方面，NIOS II的串口编程等都有值得参考的地方。最好使用QUARTUS7.2编译，目标芯片是选用EP1C6Q240-This is my graduation project SVPWM make a permanent magnet AC synchronous motor control system, which apart from a driver SVPWM algorithm, there is a stepper motor controller, as well as QUARTUS7.2 based on the NIOS II control core, through PC serial port can be controlled permanent magnet AC synchronous motor and stepper motor for accurate positioning. The system is more complicated, the use of more knowledge, in the SVPWM algorithm, PID algorithm, stepper motor control, NIOS II serial programming, such as places are worth considering. QUARTUS7.2 compile the best use of the target chip is optional EP1C6Q240
- 2023-05-08 19:40:04下载
- 积分：1
-
test2
说明： 试用Verilog HDL语言，设计十进制计数器，将计数过程用一个数码管进行显示（0～9）。要求首先使用Modelsim软件进行功能仿真，然后使用Quartus软件综合，并下载到开发板进行电路功能测试。(Using Verilog HDL language, a decimal counter is designed. The counting process is displayed by a digital tube (0 ~ 9). It is required to first use Modelsim software for functional simulation, then use quartus software for synthesis, and download to the development board for circuit functional test.)
- 2020-05-17 11:07:28下载
- 积分：1
-
flash
本程序是fpga控制flash的读写程序，包括了程序和仿真时的测试文件(fpga flash)
- 2013-07-21 14:47:36下载
- 积分：1
-
Verilog
说明： Verilog简易教程，或者说是讲义，清晰易懂，适合初学者入门使用(Layman' s Guide to Verilog, or a lecture, legible entry to use for beginners)
- 2010-04-08 16:51:54下载
- 积分：1
-
该项目是用于执行4位arethmatic操作和逻辑操作…
The project is used to perform the operation of 4 bit arethmatic and logical operation. the projcet is implemented in spartan 3E
- 2022-03-21 15:49:24下载
- 积分：1
-
textiowrite
quartus ii 环境下，一个完整的利用TEXTIO仿真的源代码，包括读数据文件和输出数据到文件。(Under quartus ii environment, a complete simulation using TEXTIO source code, including reading data files and output data to a file.)
- 2014-02-03 23:56:30下载
- 积分：1
-
jjj
实现了四bit计数器的功能，使用的是VHDL语言描述(Four-bit counter, using the VHDL language description)
- 2012-12-20 10:53:46下载
- 积分：1
