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QPSK
In this case is a QPSK algorithm code for mapping the interleaved code, using VHDL language. This code provide the method of mapping the code by using QPSK algorithm.
- 2014-11-19 04:27:20下载
- 积分:1
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Verilog-shift-mulfunction
FPGA verilog 实现任意位宽的移位相乘法,有符号小数或者有符号整数相乘。函数调用方式(FPGA verilog achieve any bit-wide shift multiplication , signed or signed decimal integer multiplication . Function call
)
- 2014-06-21 17:08:12下载
- 积分:1
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《Verilog HDL 程序设计教程》2
《Verilog HDL 程序设计教程》2-"Verilog HDL Design Guide," 2
- 2022-03-04 04:35:38下载
- 积分:1
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altera DE1 SD_CARD带写入一个扇区功能的程序,已确认成功,下载直接运行就可以看效果...
altera DE1 SD_CARD带写入一个扇区功能的程序,已确认成功,下载直接运行就可以看效果-altera DE1 SD_CARD with a sector write function procedures, has confirmed the success of running can be downloaded directly watch the effect of
- 2022-04-16 19:05:08下载
- 积分:1
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Altera-FPGA_CPLD-design-Advanced
《Altera FPGA_CPLD设计 高级篇》详细介绍FPGA应用于高级特性,LogicLock设计,时序约束,设计优化,高级工具及系统级设计技术,是深入学习FPGA的重要材料(" Altera FPGA_CPLD advanced part design" details FPGA used in advanced features, LogicLock design, timing constraints, design optimization, system-level design tools and advanced technology, in-depth study is an important material for FPGA)
- 2017-03-08 19:47:32下载
- 积分:1
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Wishbone dma ip core
Wishbone dma ip core
- 2022-01-26 04:18:15下载
- 积分:1
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verilog-PS2
说明: 在FPGA内,实现PS2键盘数据读取功能,verilog源代码(In the FPGA, achieving PS2 keyboard data read functions, verilog source code)
- 2009-08-28 16:10:24下载
- 积分:1
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AD4003_CTR
一个AD4003的测试/控制程序,2Ms/s,18bit的AD高速AD芯片(A AD4003 test / control program, 2Ms/s, 18bit AD high speed AD chip)
- 2020-08-24 08:18:16下载
- 积分:1
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msp430x41x
低电源电压范围为1.8 V至3.6 V
超低功耗:
- 主动模式:280μA,在1 MHz,2.2伏
- 待机模式:1.1μA
- 关闭模式(RAM保持):0.1μA
五省电模式
欠待机模式唤醒
超过6微秒
16位RISC架构,
125 ns指令周期时间
12位A/ D转换器具有内部
参考,采样和保持,并
AutoScan功能
16位Timer_B随着三† 或七‡
捕捉/比较随着阴影寄存器
具有三个16位定时器A
捕捉/比较寄存器
片上比较器
串行通信接口(USART),
选择异步UART或
同步SPI软件:
- 两个USART(USART0 USART1)的†
- 一个USART(USART0)‡
掉电检测
电源电压监控器/监视器
可编程电平检测
串行板载编程,
无需外部编程电压
安全可编程代码保护
融合(Low Supply-Voltage Range, 1.8 V to 3.6 V
Ultralow-Power Consumption:
− Active Mode: 280 µ A at 1 MHz, 2.2 V
− Standby Mode: 1.1 µ A
− Off Mode (RAM Retention): 0.1 µ A
Five Power Saving Modes
Wake-Up From Standby Mode in Less
Than 6 µ s
16-Bit RISC Architecture,
125-ns Instruction Cycle Time
12-Bit A/D Converter With Internal
Reference, Sample-and-Hold and
Autoscan Feature
16-Bit Timer_B With Three† or Seven‡
Capture/Compare-With-Shadow Registers
16-Bit Timer_A With Three
Capture/Compare Registers
On-Chip Comparator
Serial Communication Interface (USART),
Select Asynchronous UART or
Synchronous SPI by Software:
− Two USARTs (USART0, USART1)†
− One USART (USART0)‡
Brownout Detector
Supply Voltage Supervisor/Monitor With
Programmable Level Detection
Serial Onboard Programming,
No External Programming Voltage Needed
Programmable Code Protection by Security
Fuse)
- 2012-05-31 15:26:33下载
- 积分:1
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FPGA驱动VGA接口显示字符
FPGA驱动VGA接口显示字符 -FPGA-driven interface VGA display characters
- 2022-08-21 10:55:12下载
- 积分:1