-
CLZ32
针对32位MIPS微处理器中CLZ指令（对单个字高位连零进行计数）的实现电路，使用了类似于超前进位的逻辑结构。包含测试文档，以及Design
Compile所用的环境和脚本。(The CLZ instruction counts the number of leading zeros in a word. The 32-bit word in the GPR rs is scanned from most-significant to least-significant bit.The number of leading zeros is counted and the result is written to the GPR rd. If
all 32 bits are cleared in the GPR rs, the result written to the GPR rd is 32. )
- 2021-03-31 19:39:08下载
- 积分：1
-
Verilog HDL for Half Adder, Full Subtractor, Half Subtractor and 2x4 decoder.
Verilog HDL for Half Adder, Full Subtractor, Half Subtractor and 2x4 decoder.
- 2022-07-06 17:29:44下载
- 积分：1
-
I2C控制核设计,由VHDL语言编写,使普通I/O端口实现I2C性能
I2C控制核设计,由VHDL语言编写,使普通I/O端口实现I2C性能-I2C control of nuclear design, VHDL language, I/O ports I2C Performance
- 2023-04-17 20:45:02下载
- 积分：1
-
ldpc_decoder_802_3an_latest.tar
LDPC encoder and decoder, very simple
- 2015-03-10 05:35:38下载
- 积分：1
-
altera_reed_solomon_design
altera 的reed solomn 设计(reed solomn design from altera)
- 2009-06-14 15:39:32下载
- 积分：1
-
Its-GPS-ranging-codes
GPS信号结构,C/A码产生方式及其测距码研究(GPS signal structure and ranging code research)
- 2014-03-20 08:51:27下载
- 积分：1
-
ptos
八位并行数据转换为串行数据依时钟信号串行输出(Eight bit parallel data to serial data)
- 2018-05-02 19:43:25下载
- 积分：1
-
This is a JPEG codec the VHDL code
这是一个JPEG的编解码的VHDL程序代码-This is a JPEG codec the VHDL code
- 2023-05-21 08:00:03下载
- 积分：1
-
数字式移相信号发生器可以产生预置频率的正弦信号，也可产生预置相位差的两路同频正弦信号，并能显示预置频率或相位差值；...
数字式移相信号发生器可以产生预置频率的正弦信号，也可产生预置相位差的两路同频正弦信号，并能显示预置频率或相位差值；-digital phase shifting generator can produce preset frequency sinusoidal signal, Preferences may also have phase difference with the way the two-frequency sinusoidal signal, and can show that the preset frequency or phase difference value;
- 2023-07-21 04:20:04下载
- 积分：1
-
11-07-11
AD9910实现脉冲内线性调频信号，仅供参考(AD9910 to achieve linear FM pulse signal, for reference only)
- 2013-09-16 10:52:00下载
- 积分：1
