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In this case is a convolutional code on a simple algorithm, using verilog HDL la...
本例是关于卷积码的一个简单算法,用verilog HDL语言编写,整个文档包括了产生卷积的整个工程。-In this case is a convolutional code on a simple algorithm, using verilog HDL language, the entire document, including the method of deconvolution of the whole project.
- 2022-02-05 20:03:55下载
- 积分:1
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The_Ten_Commands_of_Excellent_Design
介绍了FPGA设计的十大准则,对初学者很有用,对于工作多年的同志,也会有整理总结的好处(Describes the FPGA design of the top ten criteria are useful for beginners, for many years comrades, there will be finishing the benefits of the summary)
- 2009-09-26 16:44:29下载
- 积分:1
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turbo_encoder
在赛灵思的FPGA上实现turbo码的编码程序,使用Verilog语言实现。(Implemented on Xilinx FPGA in the turbo coding principle, the use of Verilog language.)
- 2021-04-19 09:38:51下载
- 积分:1
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数字信号处理的FPGA实现-第三版-verilog源程序
数字信号处理的FPGA实现, 包括了FPGA基础知识,浮点运算,信号处理的FIR FFT等,附录包含源代码(Digital signal processing FPGA implementation, including the basic knowledge of FPGA, floating point operations, signal processing FIR, FFT, etc., the appendix contains the source code)
- 2017-08-06 17:38:33下载
- 积分:1
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华勒斯树结构的8位修正展位乘数
应用背景Booth乘法器实现快速乘法algorithm.mainly用于通信和DSP组成的3块摊位重新编码,华勒斯树和超前进位addder关键技术超大规模集成电路设计,通信和DSP的应用,芯片设计,VHDL,Verilog程序,加法器和乘法器
- 2022-02-04 19:57:10下载
- 积分:1
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王金明:《Verilog HDL 程序设计教程》程序
王金明:《Verilog HDL 程序设计教程》程序-Wang Jinming:
- 2023-04-09 20:15:03下载
- 积分:1
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pc104vhdl_change
PC104总线的CPLD代码,调试已经通过,可以修改应用到其他的工程(PC104 bus CPLD code, debugging has been passed, you can modify the application to other engineering
示例用法:)
- 2013-08-29 12:07:43下载
- 积分:1
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pulse_change
用vhdl实现脉冲宽度可控的一简单程序 仿真环境MAXPLUS-(use VHDL to achieve controllable pulse width of a simple process simulation environment Segments-)
- 2005-07-24 11:53:57下载
- 积分:1
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ps2interface
one of example about hardware design language
- 2009-12-25 07:17:18下载
- 积分:1
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LPC总线从设备的verilog设计,包含状态机和中断功能。
LPC总线从设备的verilog设计,包含状态机和中断功能。-verilog code for LPC device
- 2022-01-28 17:10:12下载
- 积分:1