登录
首页 » VHDL » 这是我在学习过程中编的数字钟的原程序,含各种时钟模块,以及计数器,累加器等,可以直接下载,已经编译通过!...

这是我在学习过程中编的数字钟的原程序,含各种时钟模块,以及计数器,累加器等,可以直接下载,已经编译通过!...

于 2022-07-19 发布 文件大小:538.65 kB
0 220
下载积分: 2 下载次数: 1

代码说明:

这是我在学习过程中编的数字钟的原程序,含各种时钟模块,以及计数器,累加器等,可以直接下载,已经编译通过!-This is my learning process in the middle of the 10-minute program, containing various clock module and the counter, accumulator, and can download, compile!

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • Quartus在自己写的TCL,分布IO的例子。
    quartus 中,自己写的tcl,分配io的例子。-Quartus in their own writing tcl, distribution io example.
    2022-03-24 02:15:21下载
    积分:1
  • fpga_dsp_simple
    dsp和fpag通信的测试程序,包含整个工程和signaltap测试信号。(the the dsp and fpag communications test procedures, including the entire the engineering and signaltap test signal.)
    2013-04-14 15:17:20下载
    积分:1
  • qpsk_demod_use_FPGA
    根据软件无线电的思想,提出了一种新颖的数字信号处理算法,对QPSK信号的相位进行数字化处理,从而实现对QPSK信号的解调.该算法允许收发两端载波存在频差,用数字锁相实现收发端载波的同步,在频偏较大的情况下,估算频偏的大小,自适应设置环路的带宽,实现较短的捕获时间和较好的信噪性能。整个设计基于XILINX公司的ISE开发平台,并用Virtex-II系列FPGA实现。用FPGA实现调制解调器具有体积小、功耗低、集成度高、可软件升级、扰干扰能力强的特点,符合未来通信技术发展的方向。(According to the idea of software radio, a novel digital signal processing algorithm, the phase of QPSK digital signal processing, enabling the demodulation of QPSK signals. This algorithm allows the sending and receiving ends of the carrier frequency difference exists, using digital phase-locked to achieve synchronization of sending and receiving end of the carrier, in the case of large frequency offset, frequency offset estimation of the size, adaptive set the loop bandwidth to achieve shorter acquisition time and better noise performance. The whole design is based on the company XILINX ISE development platform, and Virtex-II series with the FPGA. FPGA realization of a modem with a small size, low power consumption, high integration, software upgrades available, the characteristics of strong interference interference, in line with the future direction of ICT development.)
    2010-12-06 10:52:36下载
    积分:1
  • verilog黄金参考指南中文版
    说明:  Verilog 黄金参考指南是 Verilog 硬件描述语言及其语法 语义 合并以及将它应用到硬件设计的一个简明的快速参考指南。(Verilog Golden Reference Guide is a concise and fast reference guide for Verilog Hardware Description Language and its syntax and semantics merging and its application to hardware design.)
    2020-06-18 04:20:02下载
    积分:1
  • FIR filter basic verilog code for implementation
    FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation
    2022-07-11 03:20:47下载
    积分:1
  • DDR3
    spartan6 里使用DDR3IP核,有教程以及源码(spartan6 with ddr3,source and tutorial)
    2021-01-07 08:48:52下载
    积分:1
  • SMBus
    SMbus通讯协议的Verilog程序段,已通过Moldesim的仿真,可用(Verilog program segment of the SMbus communication protocol, has been through the Moldesim simulation, the available)
    2021-03-24 18:29:15下载
    积分:1
  • a Verilog HDL language used in the preparation of multi
    一个用VerilogHDL语言编写的多路解复用器-a Verilog HDL language used in the preparation of multi-channel demultiplexer
    2022-02-06 11:12:06下载
    积分:1
  • 完成的是RS422信号的计数功能,并产生一定的触发信号
    完成的是RS422信号的计数功能,并产生一定的触发信号-RS422 signals the completion of the count function, and produce a certain trigger signals
    2022-04-14 14:08:50下载
    积分:1
  • BT656_RGB
    说明:  将BT656数据流转换成RGB图像格式的数据(Converting BT656 data stream into RGB image format)
    2021-03-22 09:29:17下载
    积分:1
  • 696516资源总数
  • 106415会员总数
  • 3今日下载