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DE2_70_TV
de2 70 开发板的演示程序，verilog语言编写，视频输入输出(de2 70 development board demo program, verilog language written, video input and output)
- 2013-04-09 19:29:51下载
- 积分：1
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fifoi
基于Xilinx Vertex2的可综合的2048x10位的读写可控制FIFO模块源代码，深度可控(Based on the Xilinx Vertex2 can be integrated 2048x10-bit read and write can control the FIFO module source code, the depth of controllable)
- 2008-12-19 00:17:51下载
- 积分：1
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cordic
cordic算法，实现加减乘除、幂次方、开方的运算(CORDIC algorithm implementation, power add, subtract, multiply and divide and square root operations)
- 2020-06-29 14:00:01下载
- 积分：1
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spi_ad
FPGA与DAC芯片的SPI接口驱动，实现串行数据的传输。(Realizing the communication between FPGA and DA chip)
- 2017-06-23 12:38:22下载
- 积分：1
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juanji
FPGA的卷积编码小程序，VHDL描述，参数为2，1，7.(2,1,7 cov with VHDL.)
- 2010-09-24 20:28:22下载
- 积分：1
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RS
说明： 通过verilog hdl语言实现RS编码器与译码器的设计(Verilog hdl language through the RS encoder and decoder design)
- 2013-07-18 16:09:22下载
- 积分：1
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day8_alu_design
this is verilog code for designing ALU in fpga.
- 2014-05-29 00:19:27下载
- 积分：1
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HwLog10
用verilog写的，基于查表法实现的LOG10运算器，在Altera FPGA中应用。(It is a verilog design of LOG10 calculation unit, which is based on LUT arithmatic. And it is applicated in Altera FPGA.)
- 2021-04-07 15:59:01下载
- 积分：1
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FPGA_flash设计
我们的设计是用一个FSM控制器来控制发送什么命令，flash模块判断FSM发送过来的state信号来选择应该执行什么操作，当命令写入或者读出后，会发送一个flag_done命令，这个命令让我们判断上个指令是否完成，如果完成后FAM将发送下一个命令.(Our design uses a FSM controller to control what commands are sent. The flash module judges the state signal sent by the FSM to select what operation should be performed. When the command is written or read out, a flag_done command is sent. This command lets us judge whether the last word is finished or if the FAM will be sent after completion. The next command)
- 2018-04-21 21:37:17下载
- 积分：1
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CPLD_PWM
一个在CPLD，EPM70128上实现的PWM控制源程序。(A CPLD, EPM70128 realize the PWM control on the source.)
- 2008-07-25 12:43:39下载
- 积分：1
